1,450 questions
1
vote
0
answers
15
views
Bash script in Azure to onboard in cortex throws error related to diagnostic settings number limit
Trying to onboard my Azure subscription in Cortex Cloud, I execute the bash script in Azure bash CLI. After fixing some role issues, I now get the following error:
The limit of 5 diagnostic settings ...
- 11
0
votes
2
answers
60
views
What this error is even about? "qemu-system-arm: warning: Blocked re-entrant IO on MemoryRegion: v7m_systick at addr: 0x0"
I am using Qemu with -
qemu-system-arm \
-M mps3-an524 \
-cpu cortex-m33 \
-smp 2 \
-nographic \
-kernel firmware.elf
It is runs perfectly. UART works ...
- 63
1
vote
0
answers
43
views
How can I modify the LED PWM configuration in the UF2 bootloader for the ATSAMD51J19A?
I'm working on a project using the ATSAMD51J19A with a UF2 bootloader, which appears as a storage device over USB for easy firmware updates. Currently, the bootloader sets an LED using a PWM signal on ...
- 11
0
votes
1
answer
74
views
Null in a dereferenced Stack Pointer in Rust on Cortex-M4 (nRF52833)
When developing a Rust no_std bootloader for my micro:bit v2.21 (Cortex-M4, nRF52833), I have encountered a weird error.
The bootloader jumps to the main application using cortex_m::asm::bootstrap(sp, ...
- 1,208
-4
votes
1
answer
172
views
S32 Design Studio: Configuring Chip (S32K144)
I am starting a S32K144 based project with S32 Design Studio. I previously worked with STM32/STM32 Cube IDE and expecting somewhat similar experience here (maybe with less features).
One of the things ...
0
votes
1
answer
126
views
Does QEMU virt board really support cortex-m4 processor?
I am trying some bare metal program on cortex-M4 processor. So I try to find a QEMU virtual platform that can work with cortex-M4.
My QEMU:
QEMU emulator version 4.2.1 (Debian 1:4.2-3ubuntu6.30)
...
- 65k
0
votes
1
answer
283
views
Does Pico 2, utilizes SIMD-instructions or just loop-unrolling during arm_dot_prod_f32?
The title says almost everything. Does (Cortex-M33) RP2350 rasberry-pi-pico 2 utilizes any SIMD-instructions (at all) via DSP during arm_dot_prod_f32 or does it simply loop-unrolls? I know for certain ...
- 2,362
0
votes
0
answers
87
views
My scheduler works fine when tasks are in assembly and in startup.S but when I use separate c files for the tasks, execution loops in task1 coz. of LR
My GitHub Repository
I have coded a basic scheduler to switch between three tasks based on systick exception. It worked well enough when it was a single file startup.S (in assembly only). I wrote the ...
1
vote
0
answers
49
views
Programmatically pass device and svdFile to cortex-debug
We have a monorepo with about a dozen controller projects and are starting to move over to vscode and generally like cortex-debug a lot.
The only issue is that the number of projects x number of ...
- 719
0
votes
1
answer
81
views
Appending to an ELF file - Cortex M / GCC
I an generating an ELF file for a Cortex M MCU using GCC. I want to know if there is a way of accomplishing the following. I wish to incorporate a new function into the ELF file at a later point in ...
- 151
1
vote
1
answer
73
views
arm-none-eabi-gdb continues instead of stepping over in no-sdk baremetal assembly
In main function after nexti instruction on bl, gdb debugger continues instead of stopping. The issue does not occur in functions called by main (e.g. I can step over functions called in ...
- 41
0
votes
1
answer
53
views
Cortex M0+ Starts Throwing Hard Fault When Assigning Value to a Particular Typedef'd Struct
Strange issue I’m stumped on: have some code I’ve been working on for months with no issues (well, not this issue). But suddenly, the assignment of a value to any structure member in a typedef’d ...
- 465
2
votes
1
answer
119
views
In ARM Cortex, the stack pointer increases instead of decreasing when allocating space for a local variable
This is my C code
void user_main(void)
{
u32 asd;
osGetSysCnt(&asd);
}
This is the disassembly
void user_main(void)
{
10040230: b507 push {r0, r1, r2, lr}
u32 asd;
...
- 805
3
votes
1
answer
83
views
Memory alignment for arrays in GCC for ARM
I have the following definitions:
static char xxxx;
static uint8_t y;
I am getting the following lines in the memory map:
.bss._ZZL7createXvE4xxxx 0x200024c0 0x1
.bss._ZZL7createXvE11y ...
- 91
2
votes
1
answer
121
views
Stack is not aligned to 8 bytes on exception entry
I'm writing a mini OS for my STM32F0 board, which has a Cortex-M0 CPU based on the ARMv6-M architecture.
In particular, I'm doing the msp/psp switch after I've created the process queue for the ...
- 21
1
vote
1
answer
64
views
Unable to access ARM Cortex M3 SRAM beyond 4k
I am a newbie trying to experiment with ARM M3 boot up sequence using gdb and arm-none-eabi compiler on qemu.
I am able to run the code with the below linker and source file
MEMORY
{
MEM : ORIGIN =...
- 13
0
votes
0
answers
46
views
If I want to write code in a register-level manner, which interrupt is enabled by default?
For example, if I want to write code without libraries, do I have to enable some system interrupts?
I know that in STM32-M3, the RESET, NMI, and Hard Fault interrupts are enabled by default. However, ...
0
votes
0
answers
65
views
Cortex M self-protects its own MPU registers
Is it possible the Cortex M MPU to disable write access to its own registers for privileged code.
I want to setup the MPU once and disable MPU modifications forever. This will prevent someone to ...
1
vote
1
answer
101
views
(Cortex M4) Bad section alignment in ELF file
we have a strange issue on a Cortex M4 MCU. The compiled Firmware works if the binary is loaded with ST-LINK in the correct section, but using C-Lion and OpenOcd, The FW load operation, load also the ...
1
vote
0
answers
24
views
gnu ld linker script LONG() not placing value as expected (ARM Cortex-M3) [duplicate]
gnu .ld linker script --
I have added a MEMORY definition to hold a checksum:
_CRC_Value = 0x12345678;
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K
FLASH (rx) : ORIGIN = ...
1
vote
0
answers
42
views
ld merge all `*.str1.4` strings
I crosscompile for cortex M microcontroller using arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi
I compile using -fdata-sections and link using -Wl,--gc-sections -Wl,--sort-section=alignment
In map ...
- 1,598
1
vote
2
answers
281
views
Debug Application via SWD on Cortex-M Starting At FLASH Address Besides 0x00
I have used multiple Cortex M parts in the past, primarily using IAR as my IDE. I am currently developing a project for a Cortex M0+ part using an Eclipse-based IDE (Infineon ModusToolbox).
I'd like ...
- 465
0
votes
1
answer
97
views
How to make my address add in every interrupt function?
First of all, I use arm cm3 core chips and the function of my codes is Shift operation. For example, UART receive "f0", save "0f" to the corresponding address. Codes are below.
...
1
vote
0
answers
67
views
Does the Cortex-M55 Processor Support Shareable and Cacheable Attributes Simultaneously?
I was looking at the Cortex-M55 TRM document and came across the following statement:
'Normal shareable cacheable attributes are converted to Normal Shareable Noncacheable by the processor' (...
- 11
1
vote
1
answer
99
views
Local variable allocation crashes the stack in embedded C on cortexm4 and operating system
Details: embedded C, cortex M4 with operating system (RTX Kernel), compiled with ARM Compiler V5.06 update6 and Microlib.
Inside a periodic task there are some functons call, one is a debug function:
/...
- 317