4,701 questions
1
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How to handle N buttons with separate actions in pure C on Arduino without writing N ISR wrappers?
I'm working on an Arduino project in pure C with multiple buttons. Each button has a different action associated with it, and I want to handle button presses using interrupts.
Currently, the typical ...
- 11
0
votes
1
answer
29
views
Micropython PIO interrupt causes loop on PICO
Extract of longer program. Just to toggle the .side pin and then quit the PIO program. Causes loop and have to nuke the PICO! Loops before the 'Run' print. Thanks
TypeError: function takes 2 ...
- 45
3
votes
0
answers
77
views
After enabling an interrupt via CSRRW in RISC-V, how many instructions may execute before trap entry?
In RISC-V machine mode, when you issue a csrrw that sets a bit in mie (i.e. enabling an interrupt that is already pending), must the very next instruction immediately branch to the interrupt handler? ...
- 305
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0
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68
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Is there a way to tell TI ARM Clang not to use R14 (LR) as a scratch register?
I have a program that I wrote that has interrupts of multiple priorities. Within the body of the low priority ISR, interrupts are re-enabled so that high priority interrupts can interrupt them if ...
- 416
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votes
1
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73
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How to write userspace or kernel application that would allow me to generate a lot of asynchronous interrupts on x86_64 Linux?
I am studying a performance (progress guarantee?) problem of an x86 hypervisor software. The current hypothesis is like this. There is a high intensity of interrupt requests caused by concurrently ...
- 2,418
2
votes
1
answer
76
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Double fault when i enable interrupts (via sti)
im making an os kernel in zig (grub to boot) and im trying to get interrupts to work specifically hardware interrupts and as soon as i enable them (i have a pic, gdt and idt setup) it gives me a ...
- 103
4
votes
1
answer
131
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Simple C, TypeScript code is supposed to allow safe UART transmission between host and target, but it doesn’t - Logpoints in embedded programming
I’m following an excellent bare metal tutorial on the Arm Cortex-M4, and I ran into unexpected, somewhat intriguing trouble when trying to properly handle UART interrupts.
Setup:
Host PC: Linux x86_64,...
- 71
0
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0
answers
43
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Pin change and timer ISR on attiny85
I am trying to let an Attiny85 decode NMRA DCC signal. I have unfortunately made a mistake in PCB design and I have not used the correct external interrupt pin (PB2) for this purpose. Than I could ...
- 53
1
vote
1
answer
111
views
How to implement interrupts in pure functional languages [closed]
How would a pure functional programming language with encapsulated effects via monads (e.g. haskell) deal with interrupts?
Usually, interrupt handlers modify some global state, but accessing a global ...
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0
votes
1
answer
101
views
How does MCU get to know this interrupt it from particular pin?
I am working on interrupt and thinking about it lately. see if i configure a pin for example say PA1 as my interrupt. then while in Handler it is handling from PA1-PA9 Handler. meaning single handler ...
- 13
0
votes
1
answer
85
views
irq type mismatch on MCP23008 device in Linux 5.10 kernel
I'm trying to configure an MCP23008 gpio expander in the Linux kernel (5.10) so that, using libgpiod v2.1, I can watch for events on the GPIO pins of the MCP23008.
This devicetree snippet would seem ...
- 33
1
vote
0
answers
84
views
IDT in NASM assembly jumps to wrong address
I've been making a kernel in pure NASM assembly. And the problem lies in the IDT not jumping to the correct address and triple faulting (expected); and as shown in gdb, causes it to go at the wrong ...
- 11
0
votes
1
answer
114
views
How does BX LR work on an exception return in cortex-M processor?
On an exception entry, a ARMv7-M processor will do below things as the last step of stack pushing.
if CurrentMode==Mode_Handler then
LR = Ones(28):'0001'; <=== This is not a valid ...
- 65k
3
votes
1
answer
108
views
Is ARM Errata 838869 (“Store immediate overlapping exception return…” ) applicable to Cortex-M7?
I’m seeing contradictory information:
ARM SDEN-1068427 (Cortex-M7 errata v11.0) doesn’t list ID 838869.
STM32H7 errata sheet (ES0445 Rev 5) groups 838869 under Cortex-M4 only.
NXP MCUXpresso SDK ...
- 1,598
2
votes
1
answer
120
views
8259A PIC programming issue?
I want to write my own minimal operating system, and started off with a keyboard driver based on the tutorial of Frank Rosner (https://dev.to/frosnerd/writing-my-own-keyboard-driver-16kh).
Since this ...
- 347
0
votes
1
answer
166
views
Linux UIO IRQ related periodic CPU usage
I have an Intel Arria 10 SoC FPGA system with 5.4.104-lts Linux built with Yocto 3.3.1 and Poky.
The installed FPGA image is doing nothing more than making interrupts to an UIO device, 50 times a sec.
...
- 1
0
votes
0
answers
84
views
Does disabling/enabling interrupts require memory barriers or similar memory ordering constraints?
AFAIK part of the reason why we need the C++11 memory model (and later patches/variants) is the fact we trade various things for single threaded executions to be fast, with only one main criteria i.e. ...
- 63
2
votes
1
answer
68
views
Why set or not set the IDT when switching to protected mode?
When switching from real mode to i386 32-bit protected mode, what is the practical difference between not setting an IDT (i.e. not running an lidt instruction) or setting an empty IDT?
Which one is ...
- 88.7k
0
votes
0
answers
69
views
Why does any modification to the exception ISRs on windows cause the system to enter a page fault loop?
I have been trying to learn more about windows internals and to do that have been poking around at the kernel. I decided to try to see how interrupt handling works and placed a break point with windbg ...
- 1
1
vote
1
answer
190
views
STM32 Shell: Why does DMA not callback (Key suspect)
I'm trying to integrate a shell into an STM32 project I'm working on. I used this library and followed a tutorial to get it working.
In the current implementation, the shell_get_char() function arms ...
- 229
-1
votes
1
answer
119
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What is the purpose of the Reset entry in the ARMv7-A vector table?
In Table B1-3 (Section B1.8.1) in the ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition, the first entry (offset 0) says it is used for "Reset" in secure mode. However, the ...
2
votes
0
answers
106
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External Interrupt on Port A is affecting functionality of my other Button Inputs on STM8S103F3P6 microcontroller
I've been working on a IR based light controller using STM8S microcontroller. Using this blog as reference text I've got the IR to work on pin PA1, according to my use case.
The issue I'm facing is ...
0
votes
0
answers
45
views
ISR data cache is null until I re-deploy it (in vercel)
I'm trying to perform an ISR fetch revalidation request. I tried this:
let data=await fetch(process.env.NEXT_PUBLIC_NodeURL+'/admin/panel/api',{
next:{ revalidate: 60 }//1 minute
}).then((response)...
- 1,679
1
vote
3
answers
139
views
Checking a char buffer from UART - what is the best practice? [closed]
Which of the following is better practice (or please suggest better alternatives) when using a global buffer with DMA with UART on an STM32 embedded application (no RTOS):
Option 1:
When entering the ...
- 55
1
vote
0
answers
97
views
Semaphore incrementation from inside SIGINT handler produces weird behavior
I am trying to set up SIGINT signal handler to wake up the main thread via binary semaphore. For that, as I attach below, I set up a SIGINT handler to run handler() function which just increments ...
