590 questions
2
votes
1
answer
140
views
What is the difference between "hlt" and "jmp $" in x86 assembly
Both hlt and jmp $ seem to halt the CPU when executed, so what is the difference?
- 85
-2
votes
1
answer
100
views
CMP , DIV & MUL Questions
Last month I started to learn how to use Cheat Engine to script with zero knowledge and some things are not clear to me. My objective was to create a defense boost by dividing the damage taken by ...
0
votes
0
answers
40
views
Sequence of instructions executed by CPU to retrieve data from NIC
In cases where no DMA is available for a peripheral device such as a Network Interface Card to directly send data from the onboard buffers to system memory, how is it handled? What sequence of ...
- 33
1
vote
0
answers
45
views
Does movnt interact with lock-prefixed instructions?
I have an application that streams data using the movnt family of instructions for non-temporal write operations on regular (write-back) memory.
Then the data is handed off to a different thread for ...
- 15.1k
2
votes
1
answer
134
views
How to determine default operand size for instruction decoding x86-64
I am currently trying my hand at writing a program that decodes x86-64 instructions into assembly, but I am stuck on determining the default memory/register operand size when dealing with instructions ...
- 23
1
vote
0
answers
71
views
Unable to access mapped memory
Why can not access the memory after 0x010ff8
(gdb) br *0x0100e2
Breakpoint 1 at 0x100e2
(gdb) run
...
Breakpoint 1, 0x00000000000100e2 in ?? ()
(gdb) info proc mappings
process 2563326
Mapped address ...
- 4,797
1
vote
1
answer
568
views
How does the label in an ADRP instruction work in arm64?
Im trying to figure out how ADRP works. I have this line of code:
0x100595c74 <+0>: adrp x17, 13159
My initial understanding of ADRP is that the program adds 0x100595c74 with an integer 13159 ...
- 25
0
votes
1
answer
63
views
What is the Name of this Process Analysis Software / What Type of Software is it?
As the title describes, does anyone know any information on this specific piece of software? I would like to find the literal software in the image. But could suffice with type of software for the ...
- 41
2
votes
1
answer
125
views
Wasm instruction ambiguity for sign-extension?
Are there any differences with respect to the effect
of i64.extend32_s and i64.extend_i32_s or are they just duplicates?
I'm trying to implement a toy compiler/interpreter lib for wasm, and the ...
- 687
0
votes
0
answers
74
views
What is First Three Instructions in the Disassembled Code
What is the meaning of the first three commands being the same after most programs are disassembled? What is the meaning of the first three commands being the same after most programs are disassembled?...
- 29
0
votes
1
answer
309
views
Stm8 assembly instructions
I am trying to learn some basic fw reverse engineering but I need some help. I am complete novice when it comes to asm but I do have some background on other languages.
What does the following line do?...
- 11
1
vote
0
answers
436
views
RISC-V FENCE Instruction test
The RISC-V Instruction Set Manual in the chapter RV32I Base Integer Instruction Set specifies fence and fence.i instructions. But on official git repository (https://github.com/riscv-software-src/...
2
votes
1
answer
754
views
Clang: How do I see where and why an ud2 instruction was generated?
In a really big project of mine, Clang seems to throw in ud2 instructions at some function calls. However, even with -Wall it doesn't seem to tell me why. I am using coroutines quite heavily in that ...
- 47
1
vote
0
answers
176
views
Is there an Arm Instructions parser for Ghidra that allows to replace References?
I am trying to replace References in CodeUnits with Ghidra. The problem is that every instruction with a reference might look different e.g.:
bne LAB_00001234
or
cbz r3, LAB_00001234
My goal would ...
- 11
1
vote
1
answer
96
views
Algorithm for testing correct operation of the UNPKBU4 instruction on TMS320C66x
algorithm on testing the correct operation of the UNPKBU4 instruction in the TMS320C66x microprocessor.
I hope someone here point me to the right direction cause I am kinda stuck and I need some ...
- 11
0
votes
1
answer
265
views
Is carry flag usually cleared after Jump-Not-Carry instruction has been evaluated?
I'm writing a simple simulation of a microprocessor, and, for the JNC instruction, I am unsure if the carry bit is automatically reset after the JNC instruction. Is it (generally, although different ...
- 159
-1
votes
1
answer
2k
views
Most frequently used instructions [closed]
Every now and then I read somewhere that of all of the instruction a CPU has only very few are used most of the time, last time it was here where the author writes: "There are only a handful of ...
- 11.6k
0
votes
1
answer
472
views
How do I change the latency of an instruction in gem5?
I could access the latency of the dram but I could not find the latency of the instructions for the matrix multiplication in gem5. I have found the OpClass.hh and the file containing the all the ...
- 1
0
votes
1
answer
515
views
(x64) Where can I find CPU instructions usage statistics in contemporary programs?
I'm looking for some statistics which would tell me/show how frequently each instruction from x64 instruction set is used overall in modern programs. I have done some google searches, but I can't find ...
- 333
2
votes
1
answer
380
views
is fcvtzs d0,d0 really an AArch64 SIMD instruction?
gcc seems to classify fcvtzs d0,d0 as as SIMD instruction, but clang does not. Who is right?
$ cat toto.s
fcvtzs d0,d0
$ aarch64-linux-gnu-gcc-10 -mcpu=cortex-a53+nosimd -c toto.s
toto.s: ...
- 2,034
0
votes
0
answers
453
views
How can I count total number of instructions of a function in a WebAssembly module?
WebAssembly code consists of sequences of instructions. I am looking to identify the total number of instructions of a certain function in a WebAssembly module.
Is there an existing method to easily ...
- 1
0
votes
0
answers
269
views
how do conditional branches and instructions which update conditional flags operate in an out of order arm architecture?
I have the following sequence of instructions:
Address instr Operands
4357128L cmp {"x1", "#16"}
4357132L bne {"4356768"}
4357136L add {"w19", &...
- 33
0
votes
2
answers
2k
views
How do instructions from a program get sent to different memory levels? Are they pre-loaded when the chips are manufactured for the first time?
I had asked a question earlier on how data gets pushed to registers in the CPU
My question now is, do instructions required for program execution get moved to memory by the compiler the same way data ...
- 123
0
votes
0
answers
85
views
physical memory store location from this sequence of instructions: data overlaps into code segment? [duplicate]
Consider the assembly program snippet below and, knowing that DS = 2000H and CS = 5000H, answer the following question:
INSTRUCTION
1 MOV AX, 3245H
2 MOV DL, O0H
3 MOV CL, 0AH
4 ...
0
votes
1
answer
58
views
Significance of learning 32 bit exploitation
I'm thinking of taking EXP 301 (Windows User Mode Exploit Development) exam. And I did some research on this exam; I came around many articles which criticised the exam material for only covering 32 ...
- 380