4,043 questions
0
votes
2
answers
121
views
compare_exchange_strong failed to update the expected value
I am trying to implement a lock-free multiple-producer-single-consumer ring buffer in C++. Here is the full definition and the test code.
#include <iostream>
#include <memory>
#include <...
- 783
1
vote
2
answers
197
views
Does this execution violate the observable behavior if ignoring the OOTA?
Consider this example:
#include <iostream>
#include <thread>
#include <atomic>
int main(){
std::atomic<int> val = 0;
std::atomic<bool> flag = false;
auto t1 = std::...
- 7,618
0
votes
1
answer
315
views
Can external IO operations be considered as if seq_cst operations in the reasoning of multithreaded programs?
Consider this example:
// thread A:
start_transaction();
update_mysql();
commit_transaction(); // remove "key" from mysql tables
remove_redis_cache("key");
// thread B:
std::...
- 7,618
7
votes
1
answer
149
views
Rename temporary file after closing its file descriptor in Python
I want to atomically write files in Python. pathlib and tempfile should be used.
I have
import os
from pathlib import Path
import tempfile
def atomic_write(f: Path, data: bytes) -> None:
with ...
- 100
2
votes
1
answer
88
views
Django transaction.atomic() on single operation prevents race conditions?
Why I need to use atomic() when I have only 1 db operation inside atomic block? My AI-assistant tells me that it prevents race conditions, but I don't use select_for_update() inside. It tells that db ...
- 66
0
votes
0
answers
147
views
Do the RMW operations on `cnt` still not avoid an inconsistent status for this multiple-producer single-consumer implementation?
Looking at this implementation of multiple-producer single-consumer, which was the implementation in Rust's standard library; however, its memory order model is derived from C++. So, it should be ...
- 7,618
3
votes
1
answer
234
views
Which memory ordering to use in lockless linked-list stack pop() implementation?
I stumbled into an interesting issue -- when it comes to intrusive lockless stacks (single-linked lists) it seems there is a consensus on how push() should look like. All internet/AI searches (and ...
- 3,457
0
votes
1
answer
174
views
Is this a conforming observable behavior in the abstract machine's sense, where the load reads a value that is not currently produced
Consider this example:
#include <atomic>
#include <iostream>
#include <chrono>
#include <thread>
#include <cassert>
int main(){
std::atomic<int> val = {0};
...
- 7,618
2
votes
0
answers
89
views
Too big a latency of ping-pong between two IPC processes on Sapphire Rapids Xeon with plain loads and stores, instruction order makes a big difference
I am running simple Ping/Pong between two processes A, B with shared memory:
shm_A and shm_B are in separate cache lines. Allocated with separate calls to shm_open, so probably in different pages, ...
- 7,274
1
vote
1
answer
189
views
Is sequentially consistent memory ordering strictly necessary in this readers-writers lock using only load/store, not RMW?
Consider this outline of a simple multi-threaded application. It has one writer thread, and ten reader threads.
#include <atomic>
#include <thread>
const int Num_readers{...
- 802
3
votes
1
answer
264
views
Is reordering really a useful concept for multithread program reasoning?
Consider this typical example:
// Thread 1:
r1 = y.load(std::memory_order_relaxed); // A
x.store(r1, std::memory_order_relaxed); // B
// Thread 2:
r2 = x.load(std::memory_order_relaxed); // C
y.store(...
- 7,618
5
votes
0
answers
201
views
Why is std::atomic<T> larger than T itself for user-defined structs on MSVC but not on GCC/Clang?
I was checking the size of std::atomic compared to T on different platforms (Windows/MSVC, Linux/GCC, Android/Clang).
For intrinsic types (like int, int64_t, etc.), the size of std::atomic matches the ...
- 251
0
votes
0
answers
91
views
How does a failed spinlock CAS affect out-of-order speculation and RMW reordering on weak memory architectures?
I’m trying to understand how speculative execution interacts with weak memory models (ARM/Power) in the context of a spinlock implemented with a plain CAS. Example:
// Spinlock acquisition attempt
if (...
- 1,385
-2
votes
1
answer
146
views
Is there a data visibility issue here?
class Sample
{
int a = 0;
public void Run()
{
// main thread.Assuming this is chromium task runner.
auto currentRunner = GetCurrentDefault();
somePooledRunner->PostTask(
[...
- 195
2
votes
0
answers
116
views
Is it possible on any real hardware, for the updated value of an atomic integer to become visible earlier via an indirect path than via a direct path?
Is it possible on any real hardware in the real world, for the updated value of an atomic integer written by one thread to become visible to another thread earlier via an indirect path, where a third ...
- 362
0
votes
1
answer
143
views
Why does Android SystemProperties use memory barriers like this?
I was reading the implementation of Android's system property, and I am confused why is it that the barriers are used this way.
I am looking at bionic/libc/system_properties/system_properties.cpp with ...
- 13
0
votes
1
answer
90
views
When an atomic variable becomes visible to a thread other than the writing thread, is it also immediately globally visible?
Suppose I have three threads. If x was written by thread2 and x is visible to thread1, do I have the guarantee that the latest value of x is also visible to thread3? In other words, can the new value ...
- 362
2
votes
1
answer
90
views
Is there a seq_cst sequence between different parts of an atomic object when atomic operations with different sizes mixed?
Updated:
I already know that this is a UB for ISO C, I apologize for the vague statement I made earlier.
This question originates from my previous question
Can atomic operations of different sizes be ...
- 563
2
votes
1
answer
195
views
Can atomic operations of different sizes be mixed?
For the same memory address, if I use atomic operations of different widths to operate on it (assuming the memory is aligned), for example(Assuming the hardware supports 128 bit atomic operations):
#...
- 563
0
votes
2
answers
218
views
Why is an acquire barrier cannot stop a reordering around a branch?
I was testing the behavior of the control dependencies in LINUX KERNEL MEMORY BARRIERS, and had a problem with the location of the fence.
I was testing this on AArch64 on a Qualcomm Snapdragon 835, ...
- 13
10
votes
1
answer
903
views
Is CPP TrivialCopyable class effectively a C struct?
During coding of std::atomic, CAS, etc, I always struggle to memorize the definition of CPP class being "TriviallyCopyable".
Now I am gradually switching to C world, I accidentally found ...
- 2,281
2
votes
1
answer
117
views
Strange behaviour of atomicCAS when used as a mutex
I'm trying to learn CUDA programming, and recently I have been working on the lectures in this course: https://people.maths.ox.ac.uk/~gilesm/cuda/lecs/lec3.pdf, where they discussed the atomicCAS ...
- 710
2
votes
1
answer
141
views
This MPSC Queue (Multi Producer Single Consumer Queue) keeps on waiting in the consumer side sometimes although I have used CAS operations
This MPSC Queue (Multi Producer Single Consumer Queue) keeps on waiting in the consumer side sometimes although I have used CAS operations. I have added CAS operation for the enqueue function. Since I ...
1
vote
1
answer
189
views
Cross-platform 128-bit atomic support: std::atomic vs std::atomic_ref on Clang/MSVC (macOS ARM64, Windows x64, Linux)
Background
I'm building a cross-platform atomic abstraction layer to support 64-bit and 128-bit atomic operations for the following types:
int64_t, uint64_t
__int128 (on Clang platforms)
A custom ...
- 251
0
votes
0
answers
48
views
Two potentially concurrent conflicting actions data race [duplicate]
In such code pieces example:
int value;
std::atomic<bool> flag;
//Thread 1
{
value = 1;
flag.store(true);
}
//Thread 2
{
value = 2;
if(flag.load())
std::cout <&...
- 83