77 questions
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What protocol does the LLC directory uses to synchronize parallel RFO signals?
The MESI or MOESI protocols need the LLC directory in order to work... and the directory needs to synchronize parallel RFO + snoop-invalidation calls in order for it to work
(in TSO architectures that ...
- 1,385
-1
votes
1
answer
186
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in chi cache coherence protocol, how does RN decide which READ transaction to send
In amba chi cache coherence protocol, the RN sends instructions (to HN) like ReadClean, ReadNotSharedDirty, ReadShared, ReadUnique, etc. But the CPU has sent only a READ instruction to the RN, so how ...
- 4,573
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1
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73
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MESI Protocol State Transition if Index Bits are Same but Tags differ
I'm trying to solve a MESI Cache problem. I have four processors (P0, P1, P2, P3) each with 4 states set to Invalid. Offset bits are to be ignored. If I read on P0 on address 11010 with two index bits ...
0
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2
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139
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Why race condition occurs when hardware has ensured coherency
#include <iostream>
#include <thread>
#include <vector>
#include <chrono>
#include <mutex>
using namespace std::chrono;
const int nthreads = 4;
const int64_t ndata = ...
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2
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147
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MESI: why we need write-miss to move from shared to modified
The book "Computer Architecture", by Hennessy/Patterson, 6th ed, on page 394, includes an example with true sharing and false sharing misses with 2 processors.
here is the example from the ...
- 1
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2
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260
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MOESI Protocol: What happens when Owned is dirty and other processors read the line in Shared?
I've been thinking about the "owned" state of the MOESI protocol. So let's say the following situation exists:
P0 has line A in O state.
P1 has line A in S state.
P0 writes to line A in its ...
- 559
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107
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Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?
Let's say we have CPU-X and CPU-Y which have their own L1d caches. First, on CPU-X we execute simple read operation on memory location M that is stored in DRAM: after that CPU-X loads value stored in ...
- 867
2
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0
answers
94
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Invalidation of an Exclusive cache line
What happens if a CPU receives an invalidation message for a cache line in the Exclusive state? Can this message enter the invalidation queue?
If so, what happens if the same CPU attempts to to that ...
- 197
1
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0
answers
156
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Confusing "Memory Barrier Example 1" in 《Memory Barriers: a Hardware View for Software Hackers》？
I am reading the great paper 《Memory Barriers: a Hardware View for Software Hackers》 written by Paul E. McKenney, which helps me a lot. But I came across a doubt in 《6.2 Example 1》:
The author has ...
- 49
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2
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256
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How is message queue implemented in cache coherence protocol?
In Paul McKenny's famous paper "Memory Barriers: A Hardware View for Software Hackers"
3.3 Store Buffers and Memory Barriers
To see the second complication, a violation of global
memory ...
- 1,564
0
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0
answers
162
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Data races with MESI optimization
I dont really understand what exactly is causing the problem in this example:
Here is a snippet from my book:
Based on the discussion of the MESI protocol in the preceding section, it would
seem that ...
- 384
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0
answers
205
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cache coherence - Why are some steps considered exclusive?
Given this prelude:
consider a system with 2 cores, P1 and P2 using write back and write
allocate schemes.
the addresses A1 and A2 are mapped to the same cache block but A1 IS
not equal A2. Initial ...
- 582
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104
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Cache coherence systems from a timing point of view
When reading about cache coherence systems (e.g. MESI) I've not a clear understanding about the timing involved.
Consider the case in which a Core1 wants to write to a cache line in state MESI S on ...
- 313
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1
answer
640
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Why is cache coherency important in multi-processor system?
Multiprocessor systems have some kind of cache coherency protocols built into them e.g. MSI, MESI etc. The only case where cache coherency matters is when instructions executing in two different ...
- 45
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1
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257
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MSI: When shared and invalid states can occur at the same time
So, as the title says, is it possible that Processor 0 has line A with a Shared (S) state, and Processor 1 has line B with an Invalid (I) state?
Imagine the following situation:
P0: Line A | ...
- 343
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1
answer
314
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Is synchronization faster on the same physical CPU core?
I have a question. If a thread modifies a variable, will the thread on the same physical core (a different hyperthread core) see the modification earlier than other cores? Or it has to wait until all ...
6
votes
1
answer
2k
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Cache coherency(MESI protocol) between different levels of cache namely L1, L2 and L3
This is about cache coherency protocol across different layers of cache. My understanding(X86_64) about L1 is that, it is owned exclusively by a core and L2 is between 2 cores and L3 for all the cores ...
- 470
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0
answers
62
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Are all processor cores on a cache-coherent system required to see the same value of a shared data at any point in time
From what I've learnt, cache coherence is defined by the following 3 requirements:
Read R from an address X on a core C returns the value written by the most recent write W to X on C if no other core ...
- 2,497
8
votes
1
answer
3k
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What cache coherence solution do modern x86 CPUs use?
I am somewhat confused with what how cache coherence systems function in modern multi core CPU. I have seen that snooping based protocols like MESIF/MOESI snooping based protocols have been used in ...
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2
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1k
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MESI Protocol & std::atomic - Does it ensure all writes are immediately visible to other threads?
In regards to std::atomic, the C++11 standard states that stores to an atomic variable will become visible to loads of that variable in a "reasonable amount of time".
From 29.3p13:
Implementations ...
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3
votes
2
answers
988
views
In MESI cache coherence protocol, when exactly does the state of a cache line change if the data needs to be fetched from memory?
In MESI protocol when a CPU:
Performs a read operation
Finds out the cache line is in Invalid state
There is no other non-invalid copies in other caches
It will need to fetch the data from the ...
6
votes
1
answer
706
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Why can the MESI protocol not guarantee atomicity of CMPXCHG on x86 without the LOCK prefix?
I understand that the MESI protocol successfully guarantees the same view of memory (caches) for different cores. My question comes from the fact that during writing MESI guarantees that the cache is ...
- 183
1
vote
1
answer
108
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MESI protocol snoop implementation issue
I have a MESI protocol question. Assume that I have two cores (core 1 and 2) and each core has its own l2 cache. When two core has the same data and cache lines are in status S, meaning they both have ...
- 109
1
vote
1
answer
879
views
x86 MESI invalidate cache line latency issue
I have the following processes , I try to make ProcessB very low latency so I use tight loop all the time and isolate cpu core 2 .
global var in shared memory :
int bDOIT ;
typedef struct XYZ_ {
...
- 1,718
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votes
0
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462
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What kind of cache coherence protocols are MSI, MESI, MOSI, MOESI and MESIF?
I was wondering what kind of protcols are those I mentioned above. More precisely my question is: are they Write-Update or Write-Invalidate? Or it depends on their implementation? Thanks
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