In a System Verilog FSM can a repetitive State be converted to a Task?

Question

I'm writing an FPGA state machine in System Verilog to read bytes from a SPI port and parse them into commands to the FPGA. The "RXSPIBITS" state is used to read SPI bytes by multiple other states like "GetCommand" and "GetParams" so I've had to set up a ReturnState mechanism to tell the RXSPIBITS state where to return control.

Can a System Verilog TASK be used to encapsulate the RXSPIBITS state code to make it more easily reusable and callable from multiple other states?

Currently the state machine's RXSPIBITS Case code looks like this.

RXSPIBITS: begin
          if (SCK_risingedge) begin
            RxBits <= {RxBits[6:0], mosi};
            BitCnt <= BitCnt + 1;
            if (BitCnt == 7) state <= returnstate;
          end
        end

So instead of entering this state 8 times I'd like to just call a GetSPIByte TASK once and have the result returned to the code in the Task's calling state.

I've searched for answers but get conflicting results about whether this would be synthesizible in System Verilog. If it matters I'm using the Gowin IDE synthesizer.

dave_59 · Accepted Answer · 2025-09-04 20:25:40Z

1

Any piece of synthesizable code can be encapsulated within a function that either returns a void or a non-void type. Functions have the capability to reference signals defined within the module in which they are declared without the need to pass them as function arguments. The code inside the function gets in-lined in the place where the function gets called.

You can use a task, but I would advise against it. If used in combinational logic, SystemVerilog doesn’t look inside the task code to determine which signals it needs to be sensitive to; it only considers its arguments. Instead, use a function with a void return type. Only use tasks that have the potential to be time-consuming (i.e., contain blocking statements).

answered Sep 4 at 20:25

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

Collectives™ on Stack Overflow

In a System Verilog FSM can a repetitive State be converted to a Task?

1 Answer 1

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

Comments

Your Answer

Sign up or log in

Post as a guest

Related