can we initialize arrays using parameter to define size in verilog for example I want
parameter max_neigh=8 , size = 72;
reg [0:8*max_neigh-1]neighbors = size'h010203040304050607;
//or as
reg [0:8*max_neigh-1]neighbors = (8*max_neigh-1)'h010203040304050607;
It gives error: "syntax error near 'h".
Any help will be highly appreciated!
Regards
Declaring arrays with parametrized does not generate any problem.
However from what I know you cannot use a parametrized size for a value assignment.
You can instead leave the 'size' field empty.
It would look like:
reg [0:8*max_neigh-1]neighbors = 'h010203040304050607;
If you absolutely want to use your size parameter you can do something like:
reg [0:8*max_neigh-1]neighbors = {size{1'b0}};
Which would duplicate the 1'b0 value size in the array, which would be equivalent to 72'h000000000000000000.
BONUS
Be aware that such assignment cannot be synthesised. This is worse than that in fact, the synthesis tool would not report an error, maybe a warning, but simply ignore that assignment. To initialize a register you should use a process.
For example a synchronous process would be with clk a clock input and nrst a reset signal that is active on low-level:
reg [0:8*max_neigh-1]neighbors;
wire [0:8*max_neigh-1]next_neighbors_value;
always@(posedge clk or negedge nrst)
if(~nrst)
neighbors <= {72{1'b0}};
else
neighbors <= next_neighbors_value;
And btw, 8*8 = 64 and not 72.
There is no need to put a size on a hexadecimal(or any base) number as long as you only care that it be extended by zeros and won't be used in a bit-wise expression where the actual size matters(~'h1 is not a good idea).
