6,393 questions
2
votes
2
answers
57
views
Proper way of resetting a FSM
I usually work with Xilinx FPGA boards. Based on the documentation I've reviewed and the research I've done, I try to avoid using a global reset signal in my designs as much as possible. However, let'...
- 21
2
votes
1
answer
77
views
Why is my simple ARM7 data memory on Verilog failing tests?
I'm implementing a simple ARM7 in Verilog and am currently in the process of creating a simple data memory. I've come up with something like this:
// very simple sdata implementation with 1mb~ memory
...
- 301
-1
votes
1
answer
87
views
`$display` output wrong result when caculate `-3*3`?
module te(
input a
);
reg clk;
reg [1:0]d1=2'd3;
reg signed [2:0]d2=-3'd3;
reg signed [4:0]d3;
always @(posedge clk) begin
d3<=d1*d2;
$display("%b",d3);//01111,how to know the ...
- 2,513
0
votes
0
answers
44
views
`ERROR: [VRFC 10-4982]` and `ERROR: [VRFC 10-8885]` through instantiation [duplicate]
`timescale 1ns/1ps
module ctrl(
output d0,
output reg d1,
output reg res=1'b1,
output reg d3,
output reg d4
);
reg [7:0] oper_cnt=8'd0;
reg clk;
assign d0=clk;
always @(...
- 2,513
-1
votes
1
answer
105
views
How to swap inout wires within a contained hierarchy (of which is synthesizable)?
For context, please look at my attached diagram to see what I am trying to accomplish.
Essentially, I want to swap inout wires using a contained hierarchy that will allow me to have more modular RTL ...
- 181
-3
votes
1
answer
161
views
`ERROR: [VRFC 10-2063] Module <my_task> not found while processing module instance <'Undefined'>` when using verilog task [closed]
`timescale 1ns/1ps
module m_top
(
input GCLK,
input [7:0] i_in1,
output o_out1,
output reg o_out2,
inout io_data,
output reg[7:0]yy
);
assign o_out1=5;
initial o_out2=6;
task my_task;
input a,b;
...
- 2,513
-1
votes
1
answer
73
views
How to print the correct value of a signed reg variable?
`timescale 1ns/1ps
module a(
input a,
output [7:0]tmp
);
reg signed[2:0] m;
reg [2:0] n;
initial begin
m=4;
n=4;
$display("%f",m);//-4.000000
$display("%f",n);//4.000000
end
...
- 2,513
-6
votes
1
answer
89
views
`ERROR: [VRFC 10-2951] 'xxxx' is not a constant` when use verilog case function
`timescale 1ns / 1ps
module m_top
(
input GCLK,
output o_out2,
inout io_data
);
reg [2:0] compare;
case(compare)
3'd1:begin
assign o_out2=1;
end
3'd2:begin
assign o_out2=2;
end
default:begin
...
- 2,513
2
votes
1
answer
82
views
Usage of assign: when to put it in an always or not [duplicate]
I know a lot of people have asked about when to use assign inside always, but I'm wondering if you actually have to. Is it ok to have a module where you have assign statements, but they are not inside ...
- 21
0
votes
0
answers
71
views
Why does module instantiation affect output reg value in vivado? [duplicate]
The instantiation module as below:
module second_module(
input [7:0] d,
output reg [7:0] q
);
initial
q <= ~d;
endmodule
The top module as below:
module top_module(
input [7:0] ...
- 2,513
1
vote
1
answer
79
views
Why `$monitor` output assignment result before time step?
module n;
reg [1:0]a, b;
initial begin
$monitor($time,," monitor ",a);
a=1;
a<=a+1;
#1;//assignment should happen here
end
endmodule
The expect output is:
1 monitor 2
but I got
0 ...
- 2,513
3
votes
1
answer
111
views
The simulation results of Vivado are inconsistent with those of HDLBits
I studied Verilog and do my exercises on HDLBits. I came up with a question when trying to solve this problem: https://hdlbits.01xz.net/wiki/Exams/2014_q3fsm
I wrote the following codes according to ...
- 53
1
vote
2
answers
119
views
Confusion about nonblocking assignments to signals for synchronous logic
I have Verilog code like this:
module gen_bits(input clk, input clear, input ld, input in, output reg[7:0] out);
always @(posedge clk) begin
if (clear)
out <= 8'b00000000;
...
- 53
2
votes
1
answer
73
views
Getting a Verilog define value on the Python side using Cocotb
I'm trying to parse all Verilog defines I have in a specific file in my Verilog code. I.e. scan through definitions like the following:
`define A 3
`define B 5
`define C (A+B)
And translate it to a ...
- 31
0
votes
0
answers
55
views
Problem with Tilelink protocol handshake between Rocket Core and a MMIO device
I am trying to add a MMIO device to rocket-chip in chipyard and I want to use Tilelink interface. This MMIO device is intended to be a slave and the rocket-core as the master. For this, I created a ...
- 182
0
votes
2
answers
148
views
Generating a PWM signal in Verilog (Quartus Prime Lite)
I'm trying to generate a pulse width modulated signal to control the power with duty cycle, but don't know where I went wrong
This is the verilog code
module pwm_generator (
input wire clk, ...
- 73
1
vote
1
answer
69
views
Unexpected Waveform Behavior During RAM Data Transfer
I currently need to read 128 8-bit data. After reading 128 data, they are combined into a 1024-bit RAM which is then assigned to dout. The ram_cnt will count from 0 to 65535. When it counts 128 (0~...
- 27
1
vote
2
answers
78
views
Is there a formal statement in the IEEE SystemVerilog standard that temporary variables can be used in procedural blocks?
I wrote a module which used the writing method like:
always_ff@(posedge clk)begin
logic [WIDTH-1:0] signal1;
........
end
When I compiled it in VCS, I drove the signal in testbench, and when I ...
- 13
3
votes
1
answer
115
views
Verilog full adder
This is the Verilog question. I have written the code according to the image, but I'm getting mismatch in the output, can I get some assistance?
module add1 ( input a, input b, input cin, output ...
- 73
1
vote
1
answer
80
views
No expected result when using Vivado. What's the problem with the testbench file?
I tried to reproduce loadable counter in Vivado 2023.1, but I cannot get expected result.
My testbench file is below:
`timescale 1ns / 1ps
module behav_counter();
reg [7:0] d;
reg clk;
reg ...
- 2,513
1
vote
1
answer
67
views
How to Fix “Net Cannot Be Assigned More Than One Value” Error When Using Multiple SPI Modules? [closed]
I'm working on a Verilog project for the DE10-Lite FPGA board that interfaces with a 3-axis accelerometer over SPI. I have separate SPI modules (spi_ee_config) for each axis: x_info, y_info, and ...
2
votes
1
answer
71
views
How do SystemVerilog VPI applications schedule in the Re-Active regions?
The SystemVerilog spec describes a scheduler model in Figure 4-1 (p. 67 of IEEE 1800-2023). It describes a number of regions, including an Active region set and a Re-Active region set.
Orthogonally, ...
- 53
1
vote
1
answer
59
views
Use different clocks in the property from the sample clock
I need to write a property to check the divisor of a fast clock. I’ve tried the following options:
property clk_frequency_P(logic pll_clk, logic destination_clk, logic clk_en, logic reset, int divisor)...
- 153
1
vote
1
answer
95
views
Using Quartus IP Catalog, how can I get predefined module name and ports order?
For the code below, I utilized a predefined RAM module from Quartus to create the RAM. How do I determine the port order when instantiating it?
I understand it must be compatible with the module from ...
- 11
4
votes
2
answers
137
views
Issue with driving an LED matrix using an FPGA (Verilog)
I am trying to run an LED matrix using an FPGA. The specifics are a TinyFPGA BX, wired into this board (driver chip datasheet), connected to this screen. Before this, I managed to drive this matrix ...
- 43