I'm trying to parse all Verilog defines I have in a specific file in my Verilog code. I.e. scan through definitions like the following:
`define A 3
`define B 5
`define C (A+B)
And translate it to a python dictionary: {'A':3, 'B':5, 'C':8}
Does Cocotb have functionality for this, or do I need to define my own parser?
I skimmed through the documentation and didn't find something supporting it, but may have missed something.
You should make your own parser if you want to do it like that. `define are value replaced by preprocessor before compilation, once instance is compiled it loose name information.
But why not using localparam instead ? localparam are seen like constants attached to module and can be read with dot notation :
module top;
localparam int A = 3;
localparam int B = 5;
localparam int C = A + B;
To read it with cocotb :
@cocotb.test()
async def test_params(dut):
a = int(dut.A)
b = int(dut.B)
c = int(dut.C)
