Questions tagged [fpga]
A Field-Programmable Gate Array (FPGA) is a logic chip consisting of an array of programmable logic blocks and interconnects that is configured by the customer after manufacturing—hence "field-programmable".
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OLED drive FPGA MIPI DSI?
I have found an OLED display on AliExpress. I have tried to find another one but this is the only one I have found with the dimensions I need, I have a proprietary video signal and need to make an ...
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On ECP5, which power pins are utilized by differential pairs?
On ECP5, which power pins are utilized by differential pairs?
Last time I checked, the datasheet is not really clear on whether the differential outputs (LVDS) are powered by VCCAUX or VCCIO. It could ...
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How to interface ADA4355 ADC with Spartan-6 SLX9 FPGA (16-bit DDR/SDR modes)?
I'm working on capturing ADC data from an ADA4355 using a Spartan-6 LX9 FPGA.
According to the ADC datasheet, it can output data in several modes, such as:
16-Bit DDR/Single Data Rate (SDR), Two-Lane, ...
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Push-pull along with pull-up
A FPGA I/O is connected to the OE# of a transceiver and I want to ensure that OE# is high (>=2V) when the system powers up and until the FPGA is configured. The system is battery powered and the ...
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CRC decoder and determining the number of error bits
I am building a hardware parallel crc_6 encoder and decoder. The polynomial I am using with the given length of input data has HD=3, meaning it can detect up to 2 error bits. The flow is at the ...
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Why are current limiting resistors enough for interfacing this PS/2 port to this FPGA?
On this Digilent/Xilinx Spartan 3e 1600 FPGA board, they use 270 ohm resistors as current limiting resistors.
In their guide they state:
The PS/2 port on the MicroBlaze Development Kit board is ...
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Series termination placement next to receiver
I have series termination resistors very close to the receiver, I have realized that they must be next to the driver (can't be moved since Im using a SOM).
The parallel HDMI input signals that go into ...
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Using LUT RAM for an array of structs in Vivado
I'm trying to synthesize the following hardware in Vivado, which contains an array of my_struct_t. To reach timing closure, it's important that this array is ...
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LCMXO640C-3TN144C Maximum Clock Frequency
I am a beginner with FPGAs and I want to find what is the maximum clock frequency where the I/O pins and PCLK pins of this FPGA "LCMXO640C-3TN144C" can work with.
MachXO Family Data Sheet ...
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Which family of FPGA to choose [closed]
I am embarking on a new project to replace simple scanning circuits. Previously this was done with a couple of 8 bit counters linked by glue logic, then driving multiplying DACs and other analog ...
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Ethernet GMII MAC to MAC Loopback
I am trying to connect two MACs in GMII mode - using a SoC to connect them, and routing GMII signals through the Fabric.
In the spec for the Intel MAC GMII IP, it assumes connection to PHY.
This IP ...
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How to open the precompiled Quartus Prime project
I have precompiled (with db and incremental_db folders, so it have sof/pof files) Quartus Prime (22.1std.1 Build 917 02/14/2023 SC Lite Edition) project and want to open "Technology Map Viewer (...
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How to achieve the lowest latency when sending and receiving data between a Linux server and an FPGA?
I am working with a Xilinx Alveo U50 FPGA and have developed an FPGA program for model inference. However, I am encountering a bottleneck in data transfer latency between Linux and the FPGA.
Currently,...
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Sending a signal to ESP32 through an FPGA using I2C protocol
I want to send a signal to ESP32 through an FPGA using I2C protocol, and I have got a problem:
Can I use the ESP32 WROOM, for example? Does it have the same reg with the same purpose as in this manual ...
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How to take a signal from GPIO pin and feed to a device with SMA input
A PCB with an FPGA is generating a pulse which is available on a JST connector GPIO pin. It is approx 30 ns wide, and repeats approx every 40,000 ns. The device for which this signal is destined has ...
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Best approach to design overcurrent monitor circuit
I have some power coming into my design, let's say 50V. I need to design a simple current monitoring (overcurrent) to detect if there is any overcurrent condition then disconnect the 50V to my load ...
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Issue VHDL custom AXI4-STREAM IP generating TLAST
I'm currently debugging a custom AXI4-Stream RTL module that I'm using to transfer data from the XADC to the DMA on a Zynq SoC. The goal of this module is to collect a fixed number of samples (...
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FPGA - Designing a parallel scrambler that also unscrambles to return original data
More details given below. My main question is, should the scrambler return the original data if the scrambled input is passed back into it? And if yes, what logic am I missing?
Apologies for the poor ...
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XCE04S2-10FFG668C Datasheet
I have the "XCE04S2-10FFG668C" xilinx FPGA but I can't find the datasheet of it. Do you know where I could a datasheet or a pinout diagram at least?
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PCIe End-Point P2P communication via Root Complex
I have two FPGAs which have PCIe gen3 x16 ports which are connected to the same root complex (and the host). I have been trying to find a way to achieve "root complex routed"/direct DMA ...
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JTAG Not Working On TE0720/TE0706/TE0790-03
I am a uni student familiar with xilinx products and I have never used trenz electronics but I can't seem to establish a connection through jtag using the trenz electronics te0720 with the te0706 ...
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PIR Motion Sensor and BASYS 3 FPGA Connection
I have been trying to create a project of adaptive light brightness using BASYS 3 FPGA and a PIR Motion Sensor HC-SR501. I connected the output of the motion sensor to a PMOD pin in the BASYS 3 to ...
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Debounce pushbutton on FPGA by using two D Flip Flop
I'm designing a module debounce pushbutton that uses 2 D Flip Flops and a Slow Clock (4Hz) and an AND Gate(Output) to ensure that the signal will generate with a single pulse. I have learned this ...
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