463 questions
2
votes
1
answer
166
views
Handling PCIe INTx interrupts (Virtual Wire Signaling) for AHCI without MSI/MSI-X (PIC-only mode)
I am writing an AHCI driver for a minimal kernel and need to handle PCIe interrupts without MSI, relying solely on the legacy PIC 8259 and PCIe INTx virtual wire signaling.
I have already implemented ...
- 23
0
votes
0
answers
72
views
How to access pcie virtual memory from kernel
I am currently using a xilinx MPSoC in a PCIe EP application. I used already successfully the the EP in a baremetal application but now I would like to port my application to linux.
So now th issue ...
- 1
2
votes
0
answers
229
views
PCIe driver, Bus Mastering DMA and dma_alloc_coherent
I a trying to write a linux-driver for a PCIe device which should have bus mastering capabilities. I am encountering the problem that the buffer space, when initialized with dma_alloc_coherent() is ...
- 33
0
votes
1
answer
402
views
How to remap PCIe Bar addresses on Linux and x86 and how is configuration space assigned MMIO? [closed]
I have doubts of how PCIe subsystem in Linux on x86 works in detail.
For as far as I know to be able to talk to a PCIe device with only mmio the following need to happen:
PCIe Configuration Space ...
- 164
0
votes
0
answers
75
views
Speed-up reading/writing operations from PCIe bus and disk using C++ on Windows
I'm developing a C++ application with GUI (Qt) for reading data from PCIe bus and writing them as binary output file on an NVMe drive. This is my actual code
void SCCCUtilityTool::...
- 89
0
votes
0
answers
62
views
PCIe MMIO Poor Access Performance
I'm testing my FPGA with PCIE4.0 X16 on Intel Xeon 6438Y+, the theoretical bandwidth is 32 GBps per direction. If I use DMA method to perform access, it can be achieved to 27GBps, which is quite ...
0
votes
1
answer
392
views
DMA Read is working but DMA write is failing
We are developing a Linux host PCIe driver for an external PCIe card(device) to perform DMA operations. DMA controller is present on the PCIe board. We need to pass the DMA address to the board via ...
0
votes
1
answer
411
views
Enumeration of multiple PCIe physical functions
I would like to understand how a linux kernel identifies that a particular PCIe device attached is supporting multiple physical functions during enumeration process? Is there a particular ...
0
votes
0
answers
56
views
Is it possible to have the PCIE DMA to 2 different memory addresses for the same call?
Like the question asks, I am tasked to find a way to have the data coming off the PCIE bus into 2 memory regions. Normally I would just do a memcpy, but I was instructed this is not possible. I don't ...
- 21
0
votes
0
answers
68
views
Recording and Checking the disk read write speed of a python program
I have created a simple python program using the pypcie package on Linux(Ubuntu) so that I can access a 1GB DDR3 memory on an fpga board through pcie. I want to test the throughput of my program when ...
- 71
0
votes
0
answers
129
views
Want to know the PCIe MMIO request payload unit size
I am searching for the unit size of the MMIO request when sending to the PCIe device BAR region from CPU.
I used this code. In the below code, you can see that the MMIO accessing code between the &...
0
votes
0
answers
159
views
How to create a PCI node in devicetree for server platforms?
Our goal is to boot linux kernel using devicetree. Implementation like bootloader pass dtb file to linux to enumerate pci and stuffs ...
In our server platforms we have multiple segments and multiple ...
0
votes
2
answers
976
views
Since PCIe write TLP is Post, what will happen when CPU access memory mapped bar address very frequently?
Since PCIe write is a Post TPL, what will happen when CPU tries to write to a memory mapped BAR address very frequently?
For example, write a busy loop and update a Register on a PCIe device.
When the ...
- 675
2
votes
1
answer
787
views
Do PCI and PCIe allow change BAR value to remap device registers to new address?
(Apologize for my previous question, a code mistake in my kernel lead to wrong values of BAR's "needed mapping space", and it misleads me written a wrong question description.)
I'm ...
- 108
3
votes
1
answer
111
views
JavaFx project using JNI C driver
I need to develop a desktop application that uses a PCI-e driver to read/write data from a FPGA board. The drivers have already been installed and I can compile the sources of the executables used for ...
- 89
0
votes
2
answers
582
views
Message data of MSI-X is useless, right?
As we know, Message data in MSI, is used to indicate which vector you are going to trigger.
But, in MSI-X, we have different Message address for different vectors. So, looks like Message data in MSI-X
...
- 1
0
votes
0
answers
943
views
How does PCIe's flow control avoid overflows with in-flight packets?
So PCIe has this mechanism where a receiver will advertise a certain amount of credits to the transmitter, that way the transmitter can check if the data that to be sent can fit in the receiver's ...
- 429
2
votes
3
answers
3k
views
PCIe ordering rules and x86, how are they compatible?
PCIe specs express clearly what are the ordering rules.
A Posted Request must not pass another Posted Request
A Posted Request must be able to pass Non-Posted Requests to avoid deadlocks
It means ...
- 2,452
0
votes
1
answer
490
views
Address of a struct used to set MSI Base address, how does it work? (in Xilinx PCIe RC driver)
Usually in PCIe RC side, the S/W should set MSI (message signaled interrupt) Base register address in the circuit right in front of the PCIe core I guess so that the PCIe core (or bridge connected to ...
- 6,139
0
votes
0
answers
1k
views
Whether PCIe Access Control Service(ACS) is enabled or disabled
How to judge whether ACS is enabled or disabled on the device? By looking at the ACS register or something else?
- 73
1
vote
1
answer
818
views
How to map physical address from /proc/iomem into user space using mmap?
I want to map PCIe Memory mapped config space into the user space. I am trying to use mmap system call to map the MMCONFIG physical address into the user space. I did some search but not able to ...
- 389
3
votes
1
answer
1k
views
macOS DriverKit: Making PCI dext to replace built-in driver
EDIT: The driver is working and has been open-sourced https://github.com/OpenMPDK/MacVFN
I'm trying to write a user-space PCI driver in DriverKit for educational/research purposes. I've found an ...
- 414
1
vote
0
answers
88
views
Question About The Sequence Of Calls To Request/Free MSI-X Interrupt Resource On FreeBSD
I have some questions about the sequence of calls to request/free MSI-X interrupt resource on FreeBSD.
I tried "amd64 FreeBSD 13.1" and "amd64 FreeBSD 13.2".
When requesting MSI-X ...
- 11
0
votes
1
answer
49
views
Drive audio card manually in C
I'm embedded programmer and using C. I wan to know how I can access audio board low level access. I know audio cards are connected to PCIe, then I must using the registers of south bridge to ...
- 410
1
vote
0
answers
112
views
Register-like PCIe framework for FPGAs?
I'm playing around with a Chinese PCI Express dev board which is based on a Xilinx Virtex-6 365T XC6VLX365T FPGA: https://www.aliexpress.com/item/4001072461753.html?gatewayAdapt=glo2fra
The demo code ...
- 70