127 questions
3
votes
1
answer
84
views
Can I somehow tell GAS to change direction of operands?
I have the binary image of a bootloader which was written with some ancient assembler.
I want to port the assembly code to GNU assembler (GAS). We speak about the X86/16-bit
(real mode) world.
This ...
- 150
3
votes
2
answers
175
views
ARM64 add instruction preferred opcode?
ARM64 supports add (extended register) that must be used for SP register, and add (shifted register) that must be used for ZR register.
The instruction add X0, X1, X2 matches the syntax for both of ...
- 524
1
vote
1
answer
174
views
8086 memory to accumulator encoding: why do mov al, [absolute] and mov ah, [absolute] have different sizes?
mov al, [10] ; a0 0a 00
mov ah, [10] ; 8a 26 0a 00
After assembling the above 8086 assembly code using NASM, I noticed a length disparity in the resulting machine code (shown in the comments above ...
0
votes
0
answers
127
views
Understanding the Funct6 field in shift immediate instruction in RISC-V
The following figure shows the instruction format of the RISC-V architecture.
Also in the following figure, that is from Computer Organization and Design, RISC-V edition, 2nd edition, the three ...
- 287
1
vote
1
answer
116
views
Writing an assembler: clean and efficient way to handle x64 REX and VEX encoding?
I'm working on an x64 assembler (just 64 bits, at least for now), and I've gotten decently far (I have support for pretty much all instructions, including most extensions), but I have some pretty ...
- 89
-1
votes
1
answer
83
views
Why does operand 1 in a modr/m byte change depending on the decoding mode
I'm trying to figure out why the instruction changes from add [eax], al to add [rax], al when changing the decoding mode from x86 to x64.
The instruction bytes are 00 00
I think it might be because ...
- 33
3
votes
1
answer
164
views
How to get NASM to encode `push` with a sign-extended 16-bit immediate?
When assembling the following with NASM:
BITS 64
push 32767
I get 68 ff 7f 00 00. This is interesting to me, since this is the 32b encoding (push dword). Any ideas why it doesn't resort to the 16b ...
- 89
2
votes
1
answer
142
views
In 68k assembler, when reading the program counter, do you get the address of the currently executing instruction or a later address?
I'm trying to understand some Motorola 68000 assembler code, and I'm getting tripped up by instructions that use the program counter. My confusion is about the effective value of the program counter ...
- 1,992
0
votes
1
answer
64
views
Why LI becomes LBU opcode after MIPS assembler
I'm trying to assemble code for MIPS R2000 (MIPS I ISA).
I'm using LI pseudo instruction to initiate a register. After running the assembler on the following code:
li $v1, 1
The binary .text ends up ...
- 365
2
votes
2
answers
311
views
Machine code layout in the memory - Intel x86
I was asked to convert the following machine code to assembly in Intel syntax:
0x421a0770: 0D 00 3D 77
0x421a0774: AC 3D 11 2A
0x421a0778: 96 AB 77 04
0x421a077c: 90 2D 0D ...
- 51
1
vote
1
answer
337
views
In shift left instruction, why is rt used as source register instead of rs?
In a shift left / shift right instruction, the rt is used as source register. Is there any reason why rt is used as source register, instead of rs ?
I saw some similar question answered "It is to ...
- 13
0
votes
1
answer
204
views
x86_64 primary opcode byte categorization
I'm in the process of writing an x86_64 disassembler, to get a better understanding of the assembly-encoding rules. I got a working version, and I understand most things about prefixes, modR/M and so ...
- 1,276
0
votes
0
answers
283
views
Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example
Confused about instruction encoding supported by my core (ie. T1, T2, etc)
Having the STM32F0 series Cortex-M0 programming manual, I found that
https://www.st.com/resource/en/programming_manual/pm0215-...
- 1,679
4
votes
0
answers
66
views
Are these push r16 encodings correct under 64BIT mode?
About push wordregister(r16) under 64BIT mode of Intel x86_64 CPU.
In B-28, Vol. 2D,
APPENDIX B, INSTRUCTION FORMATS AND ENCODINGS,
Intel Combined Manual PDF,
Order Number: 325462-080US, June 2023.
...
- 87
1
vote
1
answer
187
views
What does "input size" mean in "Compressed Displacement (disp8*N) Support in EVEX"?
In Intel(R) 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 Order Number: 325462-080US June 2023.
2.7.5 Compressed ...
- 87
0
votes
1
answer
67
views
How is data width determined for load/store instructions in Rocket Core?
I'm working on a project where we need to modify a Rocket-chip core with new instructions.
We're wondering: how does data width for load/store instructions is determined ?
For instance, LB/LH/LU have ...
- 1
3
votes
1
answer
853
views
Different encoding for arm64 "add x1, sp, x2, lsl #1" than with xzr
The add x1, sp, x2, lsl #1 instruction is supposed to be an "Add (shifted register)" but I have problems with the encoding to differentiate when SP and XZR is used. I'm astonished with the ...
- 378
0
votes
1
answer
1k
views
Why the risc-v instruction "addi sp,sp,-32" is converted to binary code "11 01"?
I'm learning risc-v instruction set. I know that "addi sp,sp,-40" will be converted to "fd810113". But I don't know why "addi sp,sp,-32" is converted to binary code "...
- 3
0
votes
1
answer
93
views
Jump addressing from PC to a target [duplicate]
Suppose we needed to jump to the memory address 0xAE87698C.
If the current PC value is 0xAF70018B show the j instruction to perform the jump
(display it as both a 32-bit binary number and as an ...
- 5
1
vote
1
answer
462
views
Opcode differences between MOV r/m32, imm32 and MOV r32, imm32
These are MOV instruction opcodes from the Intel® 64 and IA-32 Architectures Software Developer Manuals:
B8+ rd id MOV r32, imm32 OI Valid Valid Move imm32 to r32.
C7 /0 id MOV r/m32, imm32 MI Valid ...
- 1,256
5
votes
1
answer
420
views
Forcing a JMP rel32 (JMPQ)
If I do something like (dummy example):
jmp 1f
1: ret
on gcc/clang it generates a short relative jump because the label is near.
I'm curious, is it possible to force a JMP rel32 regardless of the ...
- 60.6k
0
votes
2
answers
1k
views
Why is x86 MOV two bytes, not one? How does the opcode and machine code work? [duplicate]
I'm having trouble understanding a very basic x86 instruction. The instruction is
0x080491d7 <+1>: mov %esp,%ebp
I know that it moves the value of esp into ebp. But I'm trying to ...
- 1
1
vote
1
answer
112
views
What is SignImm in Branch Target Address formula context? (BTA)
I would like to know what is SignImm in the following formula:
BTA = Branch Target Address = PC(old) + 4 + (SignImm << 2)
I have read that it is the address distance between the old PC + 4 and ...
- 325
0
votes
1
answer
1k
views
Little Endian in Instruction
I'm learning about RISC-V instructions in Computer Architecture.
What i wonder is, because of little endian, any number in RISC-V's instruction's little digit is on little bit.
I know that RISC-V use ...
- 1
3
votes
1
answer
447
views
Efficiently loading both RAX and R8 with the same small positive number
Instead of writing mov rax, 1 (7 byte encoding 48, C7, C0, 01, 00, 00, 00), I can write mov eax, 1 (5 byte encoding B8, 01, 00, 00, 00) relying on the automatic
zeroing of the high dword.
For copying ...
- 41.2k