3,575 questions
1
vote
1
answer
103
views
Does Intel CPU have instruction for paging translation result
I wonder if Intel (and Intel compatible) CPUs have an instruction (for diagnostic/debugging purposes) which, for a given linear address, returns the result of paging translation (i.e. the ...
- 144
Best practices
1
vote
2
replies
89
views
Loading a byte: Partial register stall for intel cpus (r8 vs r64)
My assembly program reads characters in a text file by loading them one by one in register 'al'. However I sometime need to use rax fully, and I think this causes a partial register stall. Now I think ...
- 43
0
votes
1
answer
62
views
Cache Allocation Technology in 13th Generation Core i9 13900E Intel CPU [closed]
I am trying to implement Cache allocation Technology`s impact with my CPU. However, when I use either lscpu to see whether my CPU supports, or cpuid -l 0x10, output is false.
How is this possible?
How ...
3
votes
1
answer
104
views
JavaFX app freezes or flickers after Intel Iris Xe driver update [closed]
I have a JavaFX desktop application that started having rendering issues after updating the Intel Iris Xe graphics driver.
On Java 11 + JavaFX (Zulu distribution):
openjdk version "11.0.25" ...
3
votes
1
answer
138
views
L1-dcache-stores, LLC-stores, cache-references and uncore memory counter don't add up in Linux perf?
I am trying to measure memory bus related performance of a simple test program on an Intel N150 (Twin Lake, which has four Gracemont cores, like Alder Lake E-cores).
PMU counters from perf stat don't ...
- 4,808
4
votes
0
answers
68
views
Why are Elevated Permissions Needed for Efficient CPU Utilization in a Multithreaded Application
On an Intel i7-13620H based computer with Windows 11, a 10-thread, compute-intensive application written in C# application uses only 4 of 10 CPU cores, seems to use only the “efficiency” (and not “...
- 733
2
votes
2
answers
173
views
Fast combined element-wise minimum/maximum for 64-bit signed integers in AVX2
I need to compute the element-wise minima and maxima of two arrays of 64-bit signed integers, using AVX2. Target is Golden Cove/Raptor Cove (Intel 12th/13th generation P-core).
AVX2 has minimum and ...
- 3,000
1
vote
0
answers
77
views
How to analyze the microarchitecture resource requirements based on the trace generated by program execution?
I'm doing an in-depth CPU microarchitectural resource analysis. I want to know the requirements of my program on processor microarchitectural resources and compare the requirements of different ...
- 455
0
votes
0
answers
68
views
How to read/write Intel MSR: IO_LLC_WAYS
I'm investigating Intel DDIO performance. Follow the official website:(https://www.intel.com/content/www/us/en/developer/articles/technical/ddio-analysis-performance-monitoring.html)
2.2.1.5 IO LLC ...
- 87
0
votes
0
answers
53
views
What is the cause of x86_64 CPU do not receive the interrupt after switching into user mode?
I want to switch into user mode from kernel mode by
switch_to_user_mode:
cli
mov ax, 0x23
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
push 0x23
push rdi
pushfq
...
- 466
0
votes
1
answer
347
views
P and E cores when doing multithreaded programming
When you split an algorithm/function/whatever to run as separate threads, let's say I launch 8 threads, you don't know that each thread is going to run on a separate one of my 8 cores, as it's the job ...
- 16.3k
1
vote
0
answers
108
views
Docker Desktop Not Responding on macOS (Intel) After Multiple Reinstalls
Body:
I am facing an issue with Docker Desktop on my MacBook (Intel) running macOS [mention your macOS version]. Despite multiple attempts to install, uninstall, and reinstall Docker, the app fails to ...
0
votes
1
answer
43
views
Recompiling the Basic Extension (e.g., instrumentation-tracer-tool) from Source Code in Intel Simics
I want to re-compile the basic extension (e.g., instrumentation-tracer-tool) from its source code in Simics 6.0.185. After installing with ispm packages, I can see a Makefile in the instrumentation-...
0
votes
0
answers
251
views
Sriov VF using IAVF PMD stops receiving traffic after restarting RX/TX queue in a DPDK application
I have a problem with stopping/starting VF RX/TX queues from our DPDK application. I am using a patched DPDK 22.11.1 and RedHat 4.14 kernel.
Traffic flows correctly until the first time we stop/start ...
-1
votes
1
answer
205
views
CMake with vcpkg - Including libbid.lib (intel math lib) as dependency for external source code (TWS API)
I'm working on a CMake C++ project using vcpkg to manage graphic package imports. The goal is to automate stock trading using the TWS API from Interactive Brokers (IBKR). Below is the current project ...
1
vote
0
answers
132
views
What is Memory Ordering Nuke in Intel CPUs?
I found this term in https://rcs.uwaterloo.ca/~ali/cs854-f23/papers/topdown.pdf
For example, incorrect data speculation
generated Memory Ordering Nukes [7] - a subset of Machine
Clears.
What is it ...
- 867
2
votes
2
answers
226
views
Can addition be done in less than a cycle when outputs depend on each other?
As you probably know modern Intel CPUs can execute 4 add instructions in one cycle assuming they are independent, and in fact Alder Lake and later can do 5 add instructions in one cycle. They also ...
1
vote
0
answers
291
views
How to build AOSP 13 at Intel 285k without errors
got constant crash with build AOSP 13 at intel 285k and 265k. (total different hardware set with different MB and memory)
OS: Ubuntu 22, Ubuntu 24
kernel: 6.8.0-49, 6.11.0-26
RAM: 96 Gb + 32 Gb swap,...
- 2,126
1
vote
1
answer
106
views
What is the proper octal representation of the encoding of the operand register in intel 8086?
The classical explanation of Intel opcodes using octal says this:
As an example to see how this works, the mov instructions
in octal are:
210 xrm mov Eb, Rb
211 xrm mov Ew, Rw
...
- 277
1
vote
1
answer
65
views
Do I need to check CPUID.01:EDX[5]?
Intel manual states that one need to check CPUID.01:EDX[5] to see if RDMSR and WRMSR instructions are available. If, using CPUID, I already found that a particular bit of a particular MSR (in my case ...
- 144
1
vote
1
answer
141
views
How can the Intel 8086 access the entirety of the address space at a given time when using memory segmentation?
The intel 8086 has a 20-line address bus. So, it can address 2^20 addresses. However, as it is easier to work with 16-bit words, the 8086 uses only 16 bits to access the memory addresses.
How is it ...
- 195
1
vote
1
answer
55
views
I have a problem with my kernel function "EXEC"
I'm writing a 16-bit x86 Assembly OS and I'm developing the program execution. The execution I've designed is different, because I want the kernel to execute the code (so it can have more control on ...
3
votes
1
answer
236
views
Setting AVX512 vector to zero/non-zero sometimes causes signal SIGILL on Godbolt
On Godbolt, this executes fine:
volatile __m512i v = _mm512_set_epi64(1, 0, 0, 0, 0, 0, 0, 0);
but all zeros does not:
volatile __m512i v = _mm512_set_epi64(0, 0, 0, 0, 0, 0, 0, 0);
It ...
- 31.1k
3
votes
0
answers
329
views
How to understand intel performance counters for evaluating cpu stalls due to memory subsystem?
I played with various Intel performance counters by directly accessing the Model Specific Registers (MSRs) on a Xeon Skylake chip, and I found some readings about the cache-miss caused stalls like ...
1
vote
1
answer
128
views
Valgrind Warning: set address range perms: large range when using -DCMAKE_BUILD_TYPE=DEBUG
I am working with a fortran program (this repository), which I compile using the newest intel LLVM compiler. This works fine when I don't supply any flags, but when I compile with -DCMAKE_BUILD_TYPE=...
- 453