0

Here I have a simple example below.

module A(o,clk,rst,i);
  output o;
  input i,clk,rst;
  ...
endmodule

and here is an interface class definition below.

interface my_if(input bit clk);
  logic o,rst,i;
  wire clk;

  clocking cb@(posedge clk);
    input o;         // why input here ?
    output i,rst;    // why output here ?
  endclocking
  ...
endinterface

My question is how to decide the signal inside cb is input or output ??

Thank you !

4
  • I mean if I may understand in this way that the direction of signal is just opposite between the module and interface ? Commented Mar 18, 2018 at 16:15
  • usually to define inputs and output views for an interface, modports are used. clocking block can be used to construct modports. The IO views are used to connect interface to different modules with different IO ports. Commented Mar 18, 2018 at 18:46
  • Thanks Serge. So the input/output view for each signals defined in interface class could be alternative, which depends on the modules we want to connect Commented Mar 18, 2018 at 19:13
  • yes, you got it. Commented Mar 18, 2018 at 19:42

1 Answer 1

2

There are many uses of input/output in SystemVerilog, which can be confusing.

For ports, they the flow of data across a boundary. For a clocking block, they represent whether a signal is passively being sampled, or actively driven. Depending on the situation, it is perfectly reasonable to have a port declared as an output, and the same signal declared as a clocking block input.

Sign up to request clarification or add additional context in comments.

Comments

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.