using interfaces in systemverilog?

Question

i have written a code in system verilog for interface. but it it giving me the error at clk. the error is Undefined variable clk.... code is error at always(posedge clk)

   interface simple_bus(input logic clk);  
     // Define the interface   
     logic req, gnt; 
     logic [7:0] addr, data; 
     logic [1:0] mode; 
     logic start, rdy; 
   endinterface: simple_bus 

   module memMod(simple_bus a); 
     // simple_bus interface port logic avail; 
     //logic clk; 
     always @(posedge clk) 
     a.gnt <= a.req & avail; 
   endmodule

when using clock in always block it is giving the error "Undefined variable: clk"

Why did you comment out the definition of the clk signal? logic clk in line 3 of memMod? You need to uncomment it so to avoid the error. Once you uncomment it, you still need to somehow drive it possibly from another always block or from a primary input port of memMod. — Ari
– Ari, Commented Jun 8, 2016 at 23:52
thank you, it worked i have made it in two ways by making as input and bit clk — venkat pasumarti
– venkat pasumarti, Commented Jun 9, 2016 at 3:40

H.Modh · Accepted Answer · 2016-06-08 10:28:54Z

1

clk is input to the given interface simple_bus, you need to hierarchically access it. Such as a.clk.

So your module code would be:

   module memMod(simple_bus a); 
     always @(posedge a.clk) 
       a.gnt <= a.req & avail; 
   endmodule

Edit:
I have tried your code at my end and it's working. PFB exa code.

interface simple_bus(input logic clk);  
     // Define the interface   
     logic req, gnt; 
     logic [7:0] addr, data; 
     logic [1:0] mode; 
     logic start, rdy; 
endinterface: simple_bus 

module memMod(simple_bus a); 
  // simple_bus interface port logic avail; 
  //logic clk; 
  always @(posedge a.clk) a.gnt <= a.req; 
endmodule

module main();
  logic clk;

  simple_bus sb(clk);
  memMod m(sb);

  initial repeat(10) clk = #5 ~clk;
endmodule

edited Jun 8, 2016 at 10:28

answered Jun 8, 2016 at 10:01

H.Modh

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2 Comments

venkat pasumarti Over a year ago

Now i am getting error at poedege a.clk Error: (vlog-13069) C:/Users/venkat/Desktop/New folder/systemverilog/second.sv(9): near ".": syntax error, unexpected '.', expecting ')'.

sharvil111 Over a year ago

@venkatpasumarthi What is avail?

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