SystemVerilog Interface multiplexer

Question

I´m new to systemverilog and trying to build a systemverilog testbench. I have a DUT that should be connected to one of two external modules via a multiplexer. I want to switch the connection during simulation and I want to use systemverilog interfaces for the connection between the DUT and the multiplexer as well as the connection between multiplexer and the two external modules. The signals in the interface are bidirectional.

I am facing trouble writing the multiplexer. I´m getting an error for the current implementation that the LHS of the expression can´t be a wire. If I change the type in the interface to logic, I get an error that this is not possible with bidirectional signals. I tried to google, but I didn´t find any tutorials on connecting interface to interface. Is this not possible? Or is there a better way of doing what I´m trying to do?

So far I have the following:

interface flash_connect_interface;
  wire interface_f_cle;
  wire interface_f_ale;
endinterface: flash_connect_interface


module flash_connect_testbench_top;     
[...]  
  // Interfaces
  flash_connect_interface flash_connect_interface_i0();
  flash_connect_interface flash_connect_interface_i1();
  flash_connect_interface flash_connect_interface_i2();

  // Connecting DUT to interface
  flash_connect flash_connect_i0(  
  .flash_connect_interface_i(flash_connect_interface_i0),
  );

  // Multiplexer  
  flash_connect_mux mux1(
  .flash_connect_interface_i_0(flash_connect_interface_i0),
  .flash_connect_interface_i_1(flash_connect_interface_i1),
  .flash_connect_interface_i_2(flash_connect_interface_i2),   
  .select(sel) 
  );

  nand_model nand_model0 (
        .Cle      (flash_connect_interface_i1.interface_f_cle),
        .Ale      (flash_connect_interface_i1.interface_f_ale),
        );

  nand_model nand_model1 (
        .Cle      (flash_connect_interface_i2.interface_f_cle),
        .Ale      (flash_connect_interface_i2.interface_f_ale),
        );  
[...]   
endmodule // end testbench_top



module flash_connect_mux(
  flash_connect_interface flash_connect_interface_i_0,
  flash_connect_interface flash_connect_interface_i_1,
  flash_connect_interface flash_connect_interface_i_2,
  input select 
  );

  always_comb begin
    // *** Here is the problem ***  
    if (select == 1'b0) flash_connect_interface_i_1 = flash_connect_interface_i_0;    
    else flash_connect_interface_i_2 = flash_connect_interface_i_0;   
  end

endmodule

Rahul Menon · Accepted Answer · 2016-08-19 18:25:38Z

1

The interfaces in this case is just bundle of wires . There seems nothing apparently wrong with your code. But if you are trying to assign interface directly to each other based on the select signal it will not work. You will need to assign all the wires individually based on the select signal. There is nothing special to mux interfaces.

The code below does the muxing.

interface flash_connect_interface;
  wire interface_f_cle;
  wire interface_f_ale;
endinterface: flash_connect_interface

module nand_model ( inout Cle , inout Ale ) ; // Sample nand model 

reg r = 1;
assign Cle = r?1:1'bz;
assign Ale = r?1:1'bz;

endmodule

module   flash_connect_mux  ( flash_connect_interface  flash_connect_interface_i_0 , flash_connect_interface flash_connect_interface_i_1 , flash_connect_interface 

flash_connect_interface_i_2 ,input [3:0] select ) ;
  // Interconnect interface assignment 
     assign flash_connect_interface_i_0.interface_f_cle = (select== 0)  ? flash_connect_interface_i_1.interface_f_cle : flash_connect_interface_i_2.interface_f_cle;
     assign flash_connect_interface_i_0.interface_f_ale =  (select== 0) ? flash_connect_interface_i_1.interface_f_ale : flash_connect_interface_i_2.interface_f_ale;
endmodule

  module flash_connect ( flash_connect_interface flash_connect_interface_i )  ;

        //check  flash_connect_interface_i.interface_f_cle ;
        //check  flash_connect_interface_i.interface_f_ale ;
  endmodule

module flash_connect_testbench_top;

reg [3:0] select ;
  // Interfaces
  flash_connect_interface flash_connect_interface_i0();
  flash_connect_interface flash_connect_interface_i1();
  flash_connect_interface flash_connect_interface_i2();

  // Connecting DUT to interface
  flash_connect flash_connect_i0(
  .flash_connect_interface_i(flash_connect_interface_i0)
  );

  // Multiplexer
  flash_connect_mux mux1(
  .flash_connect_interface_i_0(flash_connect_interface_i0),
  .flash_connect_interface_i_1(flash_connect_interface_i1),
  .flash_connect_interface_i_2(flash_connect_interface_i2),
  .select(select)
  );

  nand_model nand_model0 (
        .Cle      (flash_connect_interface_i1.interface_f_cle),
        .Ale      (flash_connect_interface_i1.interface_f_ale)
        );

  nand_model nand_model1 (
        .Cle      (flash_connect_interface_i2.interface_f_cle),
        .Ale      (flash_connect_interface_i2.interface_f_ale)
        );

endmodule // end testbench_top

Link to interface tutorial - https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/

answered Aug 19, 2016 at 18:25

Rahul Menon

7927 silver badges12 bronze badges

Sign up to request clarification or add additional context in comments.

4 Comments

Lupus Over a year ago

Thank you for your comment, but unforunately the code doesn´t completely do what I want: all the signals are bidicrectional. In my simulation, I can see the following: For select = 0, all changes on flash_connect_interface_i_1.interface_f_cle are passed on to flash_connect_interface_i_0.interface_f_cle. But not the other way around, making the connection not bidirectional anymore.

Rahul Menon Over a year ago

In case of Bi-directional signals there are generally qualifying signals which are used to trigger the change in bus direction . We could use that in the model also to do similar things.

Lupus Over a year ago

Do you mean adding this functionality into the multiplexer? Something like: if (dir=0) assign interface_i_1.interface_f_cle = interface_i_0.interface_f_cle else assign interface_i_0.interface_f_cle = interface_i_1.interface_f_cle

Rahul Menon Over a year ago

Yes something like that

Collectives™ on Stack Overflow

SystemVerilog Interface multiplexer

1 Answer 1

4 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

4 Comments

Your Answer

Sign up or log in

Post as a guest

Related