passing multidimensional array passing in systemverilog

Question

I knew that in verilog, multidimensional array cannot be passed through the module port. I heard this is allowed in systemverilog, and it is the very reason I started to use systemverilog. However, for the following code, I still encounter the error shown below for both x and y.

A reference to an entire array is not permitted in this context [Systemverilog]

Here is the code.

module Chien(p, clk, reset, load);
        wire [`m - 1 : 0] x [0 : `t - 1];
        wire [`m - 1 : 0] y [0 : `t - 1][0 : `col];
        mul_array mularray0(x, y);
endmodule

I am using ncverilog for simulation, and I take the -sv option. Is there any problem with my code, or it is the simulator's problem?

Thanks

dave_59 · Accepted Answer · 2016-03-07 15:25:21Z

2

Works fine for me in Modelsim/Questa, except you are required to declare the ports in your port list and not just have a positional list of ports.

module Chien(input wire p, clk, reset, load);

Also since I have your attention, try not to use macros in your type declarations. Better to have parameters and typedefs

package pkg;
  parameter int col = 4, m = 5, t = 6;
  typedef logic [m-1:0] array_t[t];
endpackage 

module Chien(input p, clk, reset, load);
        import pkg::*;
        wire array_t x;
        wire array_t y [col];
        mul_array mularray0(x, y);
endmodule

edited Mar 7, 2016 at 15:25

answered Mar 6, 2016 at 22:30

dave_59

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4 Comments

vim Over a year ago

I think there is a possible typo in this line: "parameter int col = 4, m = 5m t = 6; ". Shouldn't it be "parameter int col = 4, m = 5, t = 6;" ?

Nan Over a year ago

Thank you for your reply. I do not quite understand the meaning of " except you are required to declare the ports in your port list and not just have a positional list of ports." Could you please elaborate more on that? Also, I notice that you define a type called array_t, is this the trick that makes the verilog compiler accept multidimensional array?

dave_59 Over a year ago

Verilog has two styles of declaring module ports. The first is an older style where you list the port names in a positional order in the module header, followed by a declaration of port directions, followed by optional port data types. You have the port name list, but no port directions declared. That is a compiler error. The second and preferred way is to have the port order, direction, and type all declared in the module header. The array_t is not required. It is just a good programming practice when you re-use the same type in manly places.

Nan Over a year ago

I tried to change the port declaration to the one you mentioned, it still gave me the same error. So I guess it is matter of NCverilog.

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