Verilog: use array element in hierarchical path

Question

My question is about how to use predefined array element in hierarchical path in Verilog (SystemVerilog).

So for example I have defined the following string array:

string my_modules [0:1] = {"my_module_0","my_module_1"};

After, in my code I try to use them in some hierarchy:

generate
for (genvar i = 0; i < 2; i++) begin: BLOCK
    wire a = top_module.my_modules[i].a;
end
endgenerate

But I'm getting simulation error, because it cannot find the hierarchy as it is looking for my_modules module instead of its defined value (i.e my_module_0 and my_module_1).

Can someone advise on this ?

Thanks.

You cannot use strings to form variable pathnames in SystemVerilog. If you could show more of what you are trying to accomplish, we might able to suggest an alternative. — dave_59
– dave_59, Commented Aug 25, 2014 at 17:10

jclin · Accepted Answer · 2014-08-26 00:56:46Z

2

I tried with NCVerilog and the result is ok with small modification.

generate
for (genvar i = 0; i < 2; i++) begin: BLOCK
    wire a = top_module.my_modules[i][0];
end
endgenerate

There is no my_modules[i].a. How could a string type has a sub-field a?
I append [0] to my_modules[i] because my_modules[i] is a string type.

answered Aug 26, 2014 at 0:56

jclin

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2 Comments

Damo Over a year ago

This compiles at least in cadence xcelium too... thanks

Damo Over a year ago

Actually in elaboration there's a hierarchical lookup failure with this code unfortunately...

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