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I am trying to understand how interrupts work in an ARM architecture(ARM7TDMI to be specific). I know that there are seven exceptions (Reset,Data Abort, FIQ, IRQ, Pre-fetch abort, SWI and Undefined instruction) and they execute in particular modes(Supervisor, Abort, FIQ, IRQ, Abort, Supervisor and Undefined respectively). I have the following questions.

1. When the I and F bits in CPSR(status register) are set to 1 to disable external and fast interrupt, does the other 5 exceptions are also disabled ?

2. If the SWI is not disabled when I and F bits are enabled then, is it possible to intentionally trigger a SWI exception within ISR of an external interrupt?

3.When any interrupt is triggered saving the CPSR to SPSR, changing the mode is done by the processor itself. So, is it enough to write the ISR handler function and update the vector table with the handler addresses(I don't want to save r0 to r12 general purpose registers) ?

4. Whenever the mode of execution is changed does context saving happens internally by the processor(even when we change the mode manually)?

5. How to mask/disable a SWI exception?


Thank you.

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  • How exactly do you imagine things working if aborts or SWIs could be disabled? How is userspace code going to react to its syscalls being ignored? How is the CPU going to keep executing when the data/instruction it needs doesn't exist, if execution isn't diverted to a fault handler? Commented Sep 30, 2015 at 12:15
  • Hi Notlikethat, I don't know how ARM does these things. Please consider me as a beginner and I am not saying to disable them permanently. Want to know if they can be disabled, if so then how can it be done. Commented Sep 30, 2015 at 12:54
  • Ah, my comment wasn't intended as criticism, just as a proof-by-contradiction thought experiment. Disregarding any ARM-specific details, consider that interrupts (which you know can be masked) are asynchronous, whereas the other things you're asking about are triggered by executing particular instructions. Masking an interrupt prevents it happening now, but it might have only happened later anyway; Now imagine masking a synchronous event, how would you then proceed to a point where you could unmask it later, if the code in between depends on that event happening? ;) Commented Sep 30, 2015 at 13:46
  • Yes, I understand now. Thank you. Commented Sep 30, 2015 at 14:07

1 Answer 1

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  1. When the I and F bits in CPSR(status register) are set to 1 to disable external and fast interrupt, does the other 5 exceptions are also disabled ?

No, these all depend on your code to be correct. For instance, a compiler will not normally generate an swi instruction.

  1. If the SWI is not disabled when I and F bits are enabled then, is it possible to intentionally trigger a SWI exception within ISR of an external interrupt?

Yes, it is possible. You may check the mode of the SPSR in your swi handler and abort (or whatever is appropriate) if you want.

3.When any interrupt is triggered saving the CPSR to SPSR, changing the mode is done by the processor itself. So, is it enough to write the ISR handler function and update the vector table with the handler addresses(I don't want to save r0 to r12 general purpose registers) ?

No one wants to save registers. However, if you use r0 to r12 then the main code will become corrupt. The banked sp is made to store these registers. Also, the vector table is not a handler address but an instruction/code.

  1. Whenever the mode of execution is changed does context saving happens internally by the processor(even when we change the mode manually)?

No, the instruction/code in the vector page is responsible for saving the context. If you have a pre-emptable OS then you need to save the context for the process and restore later. You may have 1000s of processes. So a CPU could not do this automatically. Your context save area may be rooted in the super mode stack; you can use the ISR/FIQ sp as a temporary register in this case. For instance, the switch_to function in ARM Linux maybe helpful. thread_info is rooted in the supervisor stack for the kernel management of the user space process/thread. The minimum code (with features removed) is,

__switch_to:
    add ip, r1, #TI_CPU_SAVE                @ Get save area to `ip`.
    stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
    add r4, r2, #TI_CPU_SAVE                @ Get restore area to `r4`
    ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
    @ note the last instruction returns to a previous 
    @ switch_to call by the destination thread/process
  1. How to mask/disable a SWI exception?

You can not do this. You could write an swi handler that does nothing but increment the PC and/or you could just jump to the undefined handler depending on what it does.

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4 Comments

Nothing is done automatically the CPU as different OS architectures may have different design goals. Lots of processes, different memory spaces, low latency, etc.
Thank you for answering my questions. Could you please clarify few more points, while the interrupt triggered, the CPSR is saved into banked SPSR and the mode is changed to required mode by processor before going into handler. Correct?
In case of nested interrupts after entering the interrupt handler before enabling the interrupts it is recommended to change the mode to system mode and then enable interrupt bits(it is said that changing the mode will prevent from corrupting the lr if the external interrupt is nested multiple times). I thought changing the mode will save the context otherwise how else the lr stay safe after nested external interrupt. If the mode change does not save the context then how does nested interrupt works?
Your first comment/question is correct. Again the CPU doesn't save the registers. There is only one IRQ-lr, so if you re-enable interrupts, you must save the interrupted LR before re-enabling IRQs. Your context saving will depend on the OS model (or single task bare metal with interrupts) that you use.

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