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I’ve developed an elliptical circuit followed by 3 op-amp stages. The final output needs to go into an LPC4370 ADC (can’t be changed), which requires a differential input (100 mV to 900 mV range). I need to replace the final (3rd) op amp stage with a FDA, such that the total gain over the whole circuit is >72dB (can adjust the gains of the first 2 stages).

Inputs:

  • Input signal: 2µV - 30 uV in amplitude, nV centered at 0V. I'll assume 2µV as worst case scenario.
  • After first two op-amp stages (gains of 5 and 20): Signal is ~100 µV amplitude, centered at 27 mV

I’ve chosen to use LTC6406 simply because it’s in stock at JLCPCB, meets my specs for high gain/low noise, and I desperately need to get this design finalised, manufactured and shipped to me ASAP.

However, because I’m new to electronics, I’ve been having lots of trouble implementing it. I’ve tried two main implementations—copied directly from the FDA’s datasheet and its provided SPICE demo circuit—but can’t seem to get either working. I’ve tried adding a clamper and an AC coupling to shift the DC center voltage to 2.7 - 3.5V but unfortunately haven’t been having luck. One or both outputs (OUT+/OUT-) are often flat or not showing proper sine wave behavior.

Inputs, schematics and outputs of both implementations, and circuit requirements can be found here. But, as a summary:

Implementation 1 Implementation 1

  • OUT+: ~2.5 µV amplitude centered at 82.91mV
  • OUT-: 2.2677V (flat)

Implementation 2 Implementation 2

  • OUT+: 234.75mV
  • OUT-: 2.2675V

Requirements:

  • Keep Bode plot cutoff shape
  • Minimum of 72 dB gain
  • Final RMS noise of <7.5 mV for 100 kHz to 20 MHz
  • 5V single supply available
  • mW range power consumption

Questions:

  1. How do I bias or configure the LTC6406 properly to get a working differential output in the 100–900 mV range? The most important thing right now is to get a valid output to the ADC and I can hopefully play around with noise later.
  2. Probably a basic question, but just to confirm, for a differential ADC with a 100 mV to 900 mV input range, both OUT+ and OUT− should be centered around the same common-mode voltage (e.g. 500 mV) and be 180° out of phase? So it's fine if the signal amplitude is small (like 500 µV), as long as the common-mode and signal swing stay within the 100–900 mV range? And any outputs that don’t share a common-mode voltage wouldn’t be valid?

I’m very sorry if this is super trivial, but I’m new to electronics and have spent over a week trying to solve this, so I’m now on a ridiculously tight deadline. I would immensely appreciate any insight, advice or corrections or concerns anyone is able to offer. Thank you!

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  • \$\begingroup\$ Are you having trouble with the simulation? Or the actual circuit implementation? \$\endgroup\$ Commented Oct 16 at 17:05
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    \$\begingroup\$ You might want to double-check what noise level you expect; a negative noise figure is...not exactly reasonable. Alternately, are you sure about the total gain figure? Eyeballing resistor values, it looks like you're about 18dB short. || Is DC coupling a requirement? The input simply being off by a few mV rails the output (which may or may not manifest in the simulation; check the LMH6629 model). A couple high-pass filters eliminate that concern. \$\endgroup\$ Commented Oct 16 at 17:29
  • \$\begingroup\$ 1.8pF for C7 and C8 is not realizable in practice to any degree of accuracy due to the stray capacitances likely being comparable to that. \$\endgroup\$ Commented Oct 16 at 17:31
  • \$\begingroup\$ @CarlRutschow You sure need those caps with a 3GHz GBW amplifier. The values may need to be adjusted slightly. \$\endgroup\$ Commented Oct 16 at 17:33
  • \$\begingroup\$ The input filter noise with the 47 ohm resistors amounts to about 2.8 uVrms over the 100kHz to 20MHz band, about 3.6 uVrms over 100kHz to 30 MHz. 2.8 uVrms times a gain of 3981 (72 dB) amounts to 11 mVrms noise assuming noiseless amplifiers. With an additional amplifier noise of 1 nV/rtHz, you'll have an output noise of 26 mVrms over 100 kHz to 20 MHz. You may want to rethink your noise specifications. LTspice hint: to get total noise across the displayed bandwidth: CTRL-LMB (left mouse button) on the graph noise label (V(onoise) in this case). \$\endgroup\$ Commented Oct 16 at 18:56

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When you put several opamp amplifier stages in series with gains G1, G2... (in your case G1=5 and G2=20) then you have to think about the influence of these gains on total noise.

Each stage will amplify its own input referred noise, plus whatever noise is present in the input signal, by its gain.

Thus it's a good idea to put as much gain as possible in the first stage, in order to have highest possible signal amplitude at the input of the second stage. With a larger input signal, noise contributed by the second stage appears reduced in proportion.

Thus... your gain structure is the opposite of what it should be. Unless there's a vary good reason, you should use G1=20 and G2=5 instead of the opposite. In fact, if the opamp has enough bandwidth, using a single stage with G=100 is cheaper, simpler, and produces less noise.

However, the LMH6629 opamp you have chosen has very high bandwidth, due to being compensated for gains higher than 1. The datasheet says the SOT-23-5 package requires a minimum gain of 10 for stability, and the WSON-8 package has an extra pin to choose between minimum gains of 4 and 10.

Your circuit seems to use the SOT-23 version at a gain of 5, so it'll probably be unstable. And even using the COMP pin on WSON package to set it to a minimum gain of 4, it has a bit of peaking:

enter image description here

So, to avoid instability, you need to change your gain structure anyway. That G=5 stage won't work. It looks like LMH6629 has quite flat response at 20MHz up to G=30, so if you aim for 72dB total gain (about 4000) then you could use 3 stages with gains 30, 30, 4.4 or 20, 20, 10, or something of the sort. More gain in the first stage means better SNR, but too much gain means worse bandwidth and frequency response flatness where you need it.

So the single ended to differential stage should have a gain somewhere between 4 and 10. It is not necessary to use a super low noise opamp for this stage, because the noise it introduces will be negligible compared to what's coming of the previous stages anyway. Maybe this gives you more flexibility in opamp choice. Likewise you don't really need a 3GHz opamp.

Regarding noise, it depends if you do a tight digital bandpass filter after the ADC, or a FFT, or similar processing that only takes a small frequency range around the signal you're interested in and discards the rest of the bandwidth along with the noise at those frequencies. So even if your, say 1MHz signal is buried in wideband noise, if you apply a 10kHz wide bandpass around 1MHz, and keep only 10kHz bandwidth worth of noise in the result, SNR will improve. Then you'd only be concerned about in-band noise since the rest will be rejected. I don't know what kind of digital processing you'll use. So even though your SNR will be terrible in the raw ADC data, it may or may not be a problem, it depends on what you'll do with the acquired data.

In any case, gains should be set so noise and offset do not clip any opamp in the chain. This can be a problem, especially for offset and 1/f noise from the first opamp, so you may want to use a coupling cap between the two stages.

LMH6629 has 0.8mV max offset ; if you apply 72dB of gain on that, your last opamp will be clipping continuously which is probably what you're observing. Can't confirm without seeing the output of the second opamp, but I'm betting on enough DC offset added to your signal to clip the last opamp.

For low 1/f noise you need big (and therefore high capacitance) transistors. For a fast opamp you need low capacitance transistors in the input stage, which means small transistors. Therefore, a wide bandwidth opamp like LMH6629 will always have worse 1/F noise corner than a lower bandwidth opamp optimized for noise. This low frequency noise will be amplified like the rest and it can also clip your output opamp if you're not careful.

So you'd need AC coupling between the stages, with a high enough high pass corner to not only remove the DC offset, but also the 1/f noise from the first opamp.

I’m new to electronics

Note these fast opamps require perfect layout and decoupling. If you use a 5 ohm resistor in your feedback, then every nH of inductance counts. 1nH corresponds to 0.12 Ohm at 20MHz. Low resistor values are good for noise, but the high frequency impedance can change a lot if you just add a via or 2mm trace. Component choice is critical: you need to know the inductance of that resistor, you have to add some pF caps in the feedback to compensate for stray capacitance and their values depend on your layout, etc. Especially the 3GHz differential opamp. If it oscillates at 1GHz, do you have an instrument that can detect that?

In other words:

  • If you can pick a slower differential opamp (and you can) it'll be much easier.
  • Copy the evaluation module layout and component choice precisely.
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