-1

I am a beginner in using UVM RAL. I am trying to access by DUT Registers using UVM_BACKDOOR. I think this should not require an adapter and a predictor. I maybe wrong thinking so.

Below is my code snippet:

class my_operations extends base_test;
    `uvm_component_utils(my_operations)

    `REG_BLOCK regmodel;

    task main_phase(uvm_phase phase)
        uvm_status_e    status;
        uvm_path_e      path = UVM_BACKDOOR;

        regmodel.MY_REG.MY_REG_SIGNAL.set(1'b1);
        regmodel.MY_REG.update(status, UVM_BACKDOOR);
        assert(status == UVM_IS_OK);   // <--- Error: NULL pointer dereference

    endtask // main_phase ends here

Please show me where am I wrong?

1
  • try using write method instead of update Commented Mar 5, 2024 at 3:18

1 Answer 1

0

The `REG_BLOCK regmodel may also be defined in base class (base_test) . If base_test has a value assigned to regmodel then extending it and redefining will overwrite that value.

Removing that line will work.

Sign up to request clarification or add additional context in comments.

Comments

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.