I am a beginner in using UVM RAL. I am trying to access by DUT Registers using UVM_BACKDOOR. I think this should not require an adapter and a predictor. I maybe wrong thinking so.
Below is my code snippet:
class my_operations extends base_test;
`uvm_component_utils(my_operations)
`REG_BLOCK regmodel;
task main_phase(uvm_phase phase)
uvm_status_e status;
uvm_path_e path = UVM_BACKDOOR;
regmodel.MY_REG.MY_REG_SIGNAL.set(1'b1);
regmodel.MY_REG.update(status, UVM_BACKDOOR);
assert(status == UVM_IS_OK); // <--- Error: NULL pointer dereference
endtask // main_phase ends here
Please show me where am I wrong?