Hello I’m new to Verilog and I’ve been confused over this. In some examples the inputs and outputs are declared as wires or regs and on others they are just listed like this: Module(input a, b, output c)
What is the default data type given to these values?
The default data type for a port in any direction is an unsigned 4-state scalar (1 binary digit). In Verilog, input and inout ports must be and default to the net type wire. output ports also default to wire but can also be specified as a variable reg. (SystemVerilog relaxes some of these rules by allowing input ports to also be declared as variables).
Now that you know what the implicit defaults are, please be a good engineer and never rely on them—be explicit.
