Verilog: How to assign the output of a module to a bus which have different width

Question

Say I have a module foo with a bus input A and a bus output B:

module foo ();
    input [7:0] A;
    output [7:0] B;
endmodule

And foo is instantiated inside top module, and I want something like below(likely to have syntax error):

module top ();
     wire [2:0] bus1;
     wire [2:0] bus2;
     wire [2:0] bus3;
     wire [2:0] bus4;

     foo myfoo (
        .A[7:5](bus1[2:0]),
        .A[4:3](2'b00),
        .A[2:0](bus2[2:0]),
        .B[7:5](bus3[2:0]),
        .B[4:3](),
        .B[2:0](bus4[2:0])
     );
endmodule

What is the syntax correct and most elegant way to do that?

Serge · Accepted Answer · 2019-07-09 23:49:49Z

2

Use concats, something like the following. Use a temporary signal as a filling for the unconnected slice.

 wire tmp[1:0];

 foo myfoo (
    .A({bus1[2:0], 2'b00, bus2[2:0]),
    .B({bus3[2:0], tmp, bus4[2:0]})
 );

answered Jul 9, 2019 at 23:49

Serge

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1 Comment

user3618363 Over a year ago

Is there a way not to use "tmp" to skip the bits in the middle?

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