System Verilog array reduction gotcha and array of parameters

Question

I am trying to learn array reduction techniques in system verilog. Wrote below module:

module main;

localparam [7:0]PARAM_ARR0[3:0] = '{8'h1,8'h3,8'h4,8'h0};
localparam [3:0]PARAM_ARR1[7:0] = '{4'h3,4'h2,4'h2,4'h2,4'h1,4'h1,4'h1,4'h1};

int s = 0;
logic [7:0]arr0[3:0] = '{8'h1,8'h3,8'h4,8'h0};
logic [3:0]arr1[7:0] = '{4'h3,4'h2,4'h2,4'h2,4'h1,4'h1,4'h1,4'h1};

initial begin

//s = int'(PARAM_ARR0.sum() with (item.index<int'(PARAM_ARR1[0])?item:0));
//$display("sum0 = %0d",s);
//s = int'(PARAM_ARR0.sum() with (item.index<int'(PARAM_ARR1[4])?item:0));
//$display("sum1 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[0])?item:0));
$display("sum0 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[4])?item:0));
$display("sum1 = %0d",s);
s = int'(arr0.sum() with (item.index<int'(arr1[7])?item:0));
$display("sum2 = %0d",s);
end

endmodule

If I uncomment the first 4 lines after initial (array reduction on 2D array of parameters), VCS is throwing compile errors like below. Is array methods not applicable on parameter arrays?

    Error-[XMRE] Cross-module reference resolution error
    ../../test_param_array_sum.sv, 10
      Error found while trying to resolve cross-module reference.
      token 'sum'.  Originating module 'main'.
      Source info: PARAM_ARR0.sum(item) with (((item.index < int'(4'b1))
      ? item : 0))



    Error-[IND] Identifier not declared
    ../../test_param_array_sum.sv, 10
      Identifier 'item' has not been declared yet. If this error is not expected, 
      please check if you have set `default_nettype to none.

One more doubt is that when I simulate the code in VCS as is given above, I'm getting below results:

sum0 = 1
sum1 = 4
sum2 = 8

I was expecting results to be 0, 4 and 7 respectively. Because I was trying to get the sum of all elements in arr0 whose index is less than arr1[0] (1), arr1[4] (2), arr1[7] (3) respectively.

Thanks

vcs is correct. arrays built created from base data types do not have any functions associated with them. so, .sum() is illegal there. Try dynamic arrays instead. — Serge
– Serge, Commented May 22, 2019 at 17:14

Arun D'souza · Accepted Answer · 2019-05-23 16:21:22Z

2

This works for me in Questa 2019.2. You may have to talk to your EDA AE about what's wrong. Serge's recommendation for using dynamic arrays works: https://www.edaplayground.com/x/26RL

Also, looks like your code is giving the results you expected in Questa.

# Loading sv_std.std
# Loading work.main(fast)
# run -all
# sum0 = 0
# sum1 = 4
# sum0 = 0
# sum1 = 4
# sum2 = 7
#  quit -f
# End time: 11:17:11 on May 23,2019, Elapsed time: 0:00:21
# Errors: 0, Warnings: 0

answered May 23, 2019 at 16:21

Arun D'souza

2122 silver badges14 bronze badges

Sign up to request clarification or add additional context in comments.

1 Comment

thorondor1990 Over a year ago

Thanks for the information. Had no access to Questa or NC Sim to try. I shall speak with AE.

Collectives™ on Stack Overflow

System Verilog array reduction gotcha and array of parameters

1 Answer 1

1 Comment

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

1 Comment

Your Answer

Sign up or log in

Post as a guest

Related