different clock contraints on the same clock

Question

How can I have different clock constraints on signals in the same clock domain ?

In my design, I have a PLL which is configurable through APB registers. I am also working with 2 modes (mode1 and mode2). Depending on the mode (selectable by the user), the clock output is either 100 MHz or 70 MHz.

Because the clock come from the same PLL output, the same clock is used for the design working @100 MHz in mode 1 and @70 MHz in mode 2.

Below is the structure of the top level entity :

entity myTopLevel is
port(
I_clk : in std_logic; -- the PLL output; @100MHz or 70 MHz
I_rst : in std_logic; -- input rst   
I_mode1 : in std_logic; -- when '1' : I_clk is running @ 100 MHz, when '0' : 70 MHz
I_data : in std_logic_vector(15 downto 0);
O_data : out std_logic_vector(15 downto 0));

Inside the top level entity, there are 2 modules. 1 is running @ 100 MHz and is under reset when I_mode1 = '0'. The other is running @ 70 MHz and is under reset when I_mode1 = '1' :

INST1 : myProcessModuleMode1
port (
I_clk1 => I_clk,
I_rst1 => S_rst1, -- asserted when I_mode1 = '0'
I_data1=> I_data,
O_data1=> S_data1)

INST2 : myProcessModuleMode2
port (
I_clk2 => I_clk,
I_rst2 => S_rst2, -- asserted when I_mode2 = '0'
I_data2=> I_data,
O_data2=> S_data2)

O_data <= S_data1 when I_mode1='1' else S_data2;

However, the myProcessModuleMode2 is slower than myProcessModuleMode1. So I want to add a constraint @ 70 MHz on the module2 and 100 MHz on module1. Is it possible ? With the current version, I am constraining the clock @ 100 MHz and I get (after synthesis/ Place&Route) 90 MHz with negative slack in module 2 (which is ok, I want 70 MHz) and some negatives slacks in module 1 ... I would like to release the constraint in module 2 to get better results in module1.

Using multicycle path on module2 could be a solution with clocks @100 MHz and 50MHz and not with clocks @ 100 MHz & 70 MHz.

Note : I_mode1 (the configuration mode) is considered static. Note 2 : I_* stands for input, O_* output and S_* signal.

Regards,

A constrain does not fix the clock frequency. It tells the tool your logic requires maximum path delays to work. As this maximum decreases with rise of three clock speed, you only need to use the constraint for the fastest clock. — JHBonarius
– JHBonarius, Commented Jan 27, 2018 at 6:59
@JHBonarius: The problem is that module2 is overconstrained if the top level clock is constrained to the more demanding timing of 100 MHz. Have you tried to apply a 70 MHz constraint to the I_clk signal inside module2? The timing tool should warn about overlapping constraints and tell you which constraint was effectively applied. Maybe your tool also allows a mult cycle path constraint with non-integer multiplicity, like 1.4 ... — andrsmllr
– andrsmllr, Commented Jan 27, 2018 at 18:47
Then just connect each module to their own clock. Connect them to a data bus using clock domain crossing techniques. Why do you want to combine them in one block with one clock anyway? You're making your life complex — JHBonarius
– JHBonarius, Commented Jan 28, 2018 at 7:44
@damage : The tool doesn't allow non-integer multicycle constraints and the 70MHz constraint give me worse results in the 100MHz clock domain.@JHBonarius : I don't have any choice : the two clocks are exactly the same net (coming from the same output of the PLL which is APB configurable). I one mode this clock output is 70MHz in another mode this same output is 100MHz. If I make 2 different blocks both will have the same clock input so it's the same. — lctdim
– lctdim, Commented Jan 28, 2018 at 8:34
@damage :I will try to put the clock constraint inside the block module and let you know the results. — lctdim
– lctdim, Commented Jan 28, 2018 at 8:42

user3885596 · Accepted Answer · 2018-05-03 15:35:23Z

0

However OP has not mentioned the tool and platform, I'll show the constraints in SDC format, which is widely supported (by Synopsys, Cadence, Xilinx, Intel/Altera etc.).

Each module can have its own clock constraint through its clock input.

create_clock -name CLK1 -period 10 -waveform "0 5" [get_pins myProcessModuleMode1/I_clk1]
create_clock -name CLK2 -period 14 -waveform "0 7" [get_pins myProcessModuleMode2/I_clk2]

Now Module1 and Module2 are constrained at 100MHz and ~70MHz respectively.

Since S_data1 and S_data2 are multiplexed, there is clock domain crossing there. I would define the clocks logically exclusive to avoid timing violations between different clock domains.

set_clock_groups -logically_exclusive -group CLK1 -group CLK2

answered May 3, 2018 at 15:35

user3885596

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