VHDL Array Initialization Error

Question

I have written simple code and defined only one array. but it shows following three errors.

ERROR:HDLCompiler:806 - Syntax error near "type". Parsing entity .

ERROR:HDLCompiler:854 - Unit ignored due to previous errors. Parsing architecture of entity .

ERROR:HDLCompiler:374 - Entity is not yet compiled.

   library IEEE;
   use IEEE.std_logic_1164.all;

    type NIBBLE is ARRAY (3 downto 0) of std_ulogic;

    entity kelvin is
    end kelvin;

    architecture ospl of kelvin is
    begin
    end ospl;

Matthew · Accepted Answer · 2017-06-19 09:46:58Z

4

It is illegal in VHDL to declare a type (or anything else) outside a design unit (ie outside an entity, architecture, package or package body). Furthermore, you have to declare a type (and anything else) inside a declarative region (ie between architecture and begin or between process and begin etc).

So, your code should be

library IEEE;
use IEEE.std_logic_1164.all;

entity kelvin is
end kelvin;

architecture ospl of kelvin is
  type NIBBLE is ARRAY (3 downto 0) of std_ulogic;
begin

answered Jun 19, 2017 at 9:46

Matthew

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2 Comments

Kelvin Kalariya Over a year ago

Thank you for quickly Response. The Error I am getting now is ERROR:NgdBuild:605 - logical root block 'kelvin' with type 'kelvin' is unexpanded. Symbol 'kelvin' is not supported in target 'artix7'.

Matthew Over a year ago

@KelvinKalariya You're welcome. If you have a further question, please post it as a new question. The idea of Stack Overflow is that questions should be useful to future viewers. A conversation will not be.

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