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In systemverilog - is it possible to create an associative array of dynamic arrays?

Specifically - I need a map from id's (integers) of a certain type of request, to arrays of bytes (the response to the request), however the size of each array of bytes is only known during runtime.

If it is not possible, is there a way to have instead an associative array of pointers or pointer like objects? Or any other ideas for a solution to these types of data structures?

I know I could create a wrapper class for the arrays, but that seems a little cumbersome for such a basic need...

Thanks

1 Answer 1

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It is possible to have an associative array of dynamic arrays (or a dynamic array of dynamic arrays etc), eg:

byte AA_OF_DA_OF_BYTE [*][]; 

The trouble is that once you get more than one dimension of your dynamic array, the System-Verilog language struggles a bit and you have to start writing more code:

module ASSOC_OF_DYN;

  //
  // here's your associative array of dynamic arrays
  //

  byte AA_OF_DA_OF_BYTE [*][]; 


  // 
  // iterate over the associative array to fill it full
  //

  // eg 16 possible dynamic arrays...
  int unsigned NO_AI = 16;

  // ...of up to 256 bytes
  int unsigned MAX_DA_SIZE = 256;

  // this array is indexed by consequtive unsigned ints, but you can index by
  // whatever you like
  initial begin : FILL
    for (int AI = 0; AI < NO_AI; AI++) begin : AI_LOOP

      // pick a random size for the dynamoc array...
      automatic int unsigned DA_SIZE = $urandom_range(0, MAX_DA_SIZE-1);

      // ...and allocate the AIth dynamic array
      AA_OF_DA_OF_BYTE[AI] = new[DA_SIZE];

      // fill the dynamic array - this could be done some other way
      for (int DI = 0; DI < DA_SIZE; DI++)
        AA_OF_DA_OF_BYTE[AI][DI] = $urandom_range(0, 255);  // because it is a byte

    end : AI_LOOP
  end : FILL


  // 
  // display the filled array
  // 
  final begin : DISPLAY
    for (int AI = 0; AI < NO_AI; AI++) 
      $display("AA_OF_DA_OF_BYTE[%d]= %p", AI, AA_OF_DA_OF_BYTE[AI]);
  end : DISPLAY

endmodule

https://www.edaplayground.com/x/kZM

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4 Comments

Thanks! I'm surprised I couldn't find this answer anywhere else, since it's so straightforward
I couldn't find the reason of automatic keyword. Could you help me to understand why you declared "automatic" at // pick a random size for the dynamoc array... automatic int unsigned DA_SIZE = $urandom_range(0, MAX_DA_SIZE-1);?
@bu-ral You need to add either "automatic" or "static" here in order to comply with the IEEE 1800 standard. It doesn't matter which in this example, but not doing so is illegal. Not all simulators enforce that, though. Specifically, if you initialise a variable when you declare it inside a begin-end block, you must specify either "automatic" or "static".

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