Passing Array of Parameters through Module in System Verilog

Question

I was trying to create arrays of parameter approx and approx1 for dct8p_v5 module in system verilog. 'kcn' module has size of 6 parameter array named 'approx'. I want to pass 3 variable from 'approx' and 3 variable from 'approx1'. I tried to concatenate these two but parameter values are not propagating into kcn module. Is the syntax is correct for passing parameter array? Please let me know!

Thanks,

Farhana

module dct_8p_v5 #(parameter nb=18) (input [nb-1:0] xin [0:7] ,
                                  output [nb-1:0] xl2 [0:7]);
localparam integer approx [0:28]={3,1,1,3,0,0,0,0,3,3,1,2,0,7,7,0,7,7,3,
 3,3,10,9,9,7,7,10,9,9};
localparam integer approx1 [0:10]={8,8,8,8,8,8,9,8,8,16,16};
wire [nb-1:0] xl1 [0:7];
...
..
kcn  #(.n(nb), .approx({approx[12:14],approx1[0:2]})) kcn11(.x0(xl1[4]),.x1(xl1[7]),
.y0(xl2[4]),.y1(xl2[7]));
...
..
module kcn (x0,x1,y0,y1);
parameter n=10  ;
input [n-1:0] x0;
input [n-1:0] x1;
output [n-1:0] y0;
output [n-1:0] y1;
parameter integer approx [0:5]='{0,7,7,8,8,8};

dave_59 · Accepted Answer · 2015-08-29 22:44:34Z

1

Your code should have worked, but the array concatenation syntax has gone through a number of rule changes throughout the different revisions of the standard. You should check with your tool vendor for the current level of support of array concatenation.

answered Aug 29, 2015 at 22:44

dave_59

43.3k3 gold badges29 silver badges66 bronze badges

Sign up to request clarification or add additional context in comments.

Comments

adiles · Accepted Answer · 2015-09-08 09:34:55Z

According to clause 10.9 (IEEE1800-2012 LRM)'s description of assignment patterns:

When an assignment pattern expression is used in a right-hand expression, it shall yield the value that a variable of the data type would hold if it were initialized using the assignment pattern....

Each expression item shall be evaluated in the context of an assignment to the type of the corresponding element in the array.

So for unpacked arrays the assignment is only legal when the LHS expression's number of elements matches those in its corresponding RHS expression. In your example the LHS is a single variable expecting 6 unpacked array elements whereas the module arguments are a slice of two unpacked array variables with 3 elements each.

To get around this, I recommend using bit-stream casting in the following manner. 1) Declare the parameter a packed array.
2) For the module instance's arguments, apply a bit-stream cast to each of the sub-expressions, concatenate the result, and enclose it in an assignment pattern expression. If enclosing in an APE doesn't work, bit-stream cast the concat.

Casting in this manner requires declaring user-defined types that are size-equivalent to the integrals being casted.

Greg · Accepted Answer · 2017-12-18 20:59:28Z

0

IEEE Std 1800-2012 § 7.4.3 Operations on arrays states all arrays, packed or unpacked, can read and write to a slice of the array. There is a direct example in the LRM § 7.4.6 Indexing and slicing of arrays. However, not all simulators, synthesizers, etc., support slicing of the unpacked array. If .approx({approx[12:14],approx1[0:2]})) doesn't work, then try the expanded form: .approx('{approx[12],approx[13],approx[14],approx1[0],approx1[1],approx1[2]}) or .approx({approx[12],approx[13],approx[14],approx1[0],approx1[1],approx1[2]})

{} vs '{} for unpacked arrays described in IEEE Std 1800-2012 § 10.10 Unpacked array concatenation with examples in § 10.10.1

module dct_8p_v5 #(parameter nb=18) (
    input  [nb-1:0] xin [0:7] ,
    output [nb-1:0] xl2 [0:7] );
localparam integer approx [0:28] = '{3,1,1,3,0,0,0,0,3,3,1,2,0,7,7,
                                     0,7,7,3,3,3,10,9,9,7,7,10,9,9};
localparam integer approx1 [0:10] = '{8,8,8,8,8,8,9,8,8,16,16};
...
kcn  #(.n(nb),
       //.approx({approx[12:14],approx1[0:2]})
       .approx('{approx[12],approx[13],approx[14],approx1[0],approx1[1],approx1[2]}) // Alt
     ) kcn11(
         .x0(xl1[4]), .x1(xl1[7]), .y0(xl2[4]), .y1(xl2[7]));
...

edited Dec 18, 2017 at 20:59

answered Aug 29, 2015 at 21:45

Greg

19.3k6 gold badges51 silver badges72 bronze badges

3 Comments

dave_59 Over a year ago

When you use a '{}, that is an array assignment pattern, and each term in the pattern needs to match they type of each element of the array, in this case, each element would need to be an int, not a slice of another array. Without the ', then you have an unpacked array concatenation, and the rules are slightly different.

Greg Over a year ago

@dave_59, I missed the finer details of {} vs '{} in section 10.10 of the LRM. My answer been updated to reflect that. If the simulator/synthesizer doesn't slicing of the unpacked arrays but does support arrayed parameters, then it should accept the expanded form.

Snigdha203 Over a year ago

There are so many rules for array concatenation! I hardly get most of them. For this script I have used the following code and it worked.

kcn  #(.n(nb), .approx('{approx[12],approx[13],approx[14],approx1[0],approx1[1],approx1[2]}) ) kcn11(.x0(xl1[4]),.x1(xl1[7]),.y0(xl2[4]),.y1(xl2[7]));

This seems inefficient. I will read the concatenation rules and try whether I can pass the parameter array more efficiently or not. Thanks Farhana

Collectives™ on Stack Overflow

Passing Array of Parameters through Module in System Verilog

3 Answers 3

Comments

Comments

3 Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

3 Answers 3

Comments

Comments

3 Comments

Your Answer

Sign up or log in

Post as a guest

Related