Assigning an ID number or code to Verilog module

Question

I have designed a module (A) in Verilog and I need to instantiate it four times in a top module. The two modules communicate with each other and some other modules. 'A' sends out some signals which the other instantiation of 'A' should accept. The signals are sent through an interface or a bus. I do not want to complicate the design by incorporating any standard bus protocols. I have created an inout port to avoid having the same type of ports for input as well as output.

Is there any way to assign an id or a code to every instantiation, so that every instantiation checks for that id and accepts the signals coming from a different ID than itself. Right now without the id or a standard bus protocol, the modules are accepting their own signals too which is not supposed to happen.

toolic · Accepted Answer · 2023-04-15 10:38:37Z

Here ways you can do this:

Add an ID input port
When this port is tied to a constant, at power-up the device can detect its ID. Technically you could do dynamic ID with this, but usually you just connect the port to a constant value. This is the most flexible option, especially if you want your end product to be used as a configurable component.
```
module A ( /* your_ports */, input [1:0] ID );
/* ... code ... */
endmodule
module top;
A inst0 ( .ID(2'd0), .* );
A inst1 ( .ID(2'd1), .* );
A inst2 ( .ID(2'd2), .* );
A inst3 ( .ID(2'd3), .* );
endmodule
```
Create an ID parameter
Simulate to the ID input port except that the value is hard coded and the instance knows the ID value at compile time, before simulation or device power-up. Unique parameter values generate unique modules. If the ID is 0, it will be physically different than an ID with 1.
```
module A #(parameter ID) ( /* your_ports */ );
/* ... code ... */
endmodule
module top;
A #( .ID(0) ) inst0 ( .* );
A #( .ID(1) ) inst1 ( .* );
A #( .ID(2) ) inst2 ( .* );
A #( .ID(3) ) inst3 ( .* );
endmodule
```

Ari · Accepted Answer · 2014-04-21 16:49:52Z

Why don't you set a parameter for each module and use it as an ID? Then set the parameter uniquely for each instance:

module A;
   parameter ID = 0; //default value
   case (ID)
       0: //specific code for ID0
       1: //specific code for ID1
       2: //specific code for ID2
       3: //specific code for ID3
   endcase
endmodule

And your top module:

module top;

  A #(.ID(0)) inst_0 (...);
  A #(.ID(1)) inst_1 (...);
  A #(.ID(2)) inst_2 (...);
  A #(.ID(3)) inst_3 (...);

endmodule

A couple of other useful points:

You may want to check generate block or vectorized/array module instantiation, which allow you instantiate an array of modules.

Also, notice that in general, each module can see the entire hierarchy. Inside each module, you can access signals using a hierarchical expression:

module A;
   reg s;
   ....
   initial $display("The initial value of signal s in instance A_2 is:", top.inst_2.s);
endmodule

Beware though this is not recommended since your module description would be specific to your hierarchy.

Collectives™ on Stack Overflow

Assigning an ID number or code to Verilog module

2 Answers 2

Comments

Comments

Your Answer

Hot Network Questions

Collectives™ on Stack Overflow

2 Answers 2

Comments

Comments

Your Answer

Sign up or log in

Post as a guest

Related