Setting Variables within Makefile commands

Question

I'm facing a silly problem with GNU makefile. I want to define two targets to build a c program; one with debugging and the other without.

runNoDebug: setNoDeb objs runMe

runDebug: setDeb objs runMe

setNoDeb:
     {EXPORT} MyDEBUG= -O3

setDeb:
     {EXPORT} MyDEBUG="-DDEBUG=1 -g"

objs: cFiles
    $(CC) -o $@ $^ $(cFiles) $(CFLAGS) $(LIBS) $(MYDEBUG)

runme: objs
    ./oo

Errors arise on running this makefile, the command to set debugging executes on the subshell causing errors. If "Export" is added, the variable is defined in that subshell.

I want to define this variable in the makefile iteself to be used while building objects.

Is it possible? Or should I duplicate the "objs: cFiles" target?

possible duplicate of How can I configure my makefile for debug and release builds? — mmmmmm
– mmmmmm, Commented Jul 24, 2012 at 11:38

Chnossos · Accepted Answer · 2015-01-06 19:08:48Z

2

You need target-specific variable values :

This feature allows you to define different values for the same variable, based on the target that make is currently building.

runNoDebug: setNoDeb runMe

runDebug:   setDeb runMe

setNoDeb:   CFLAGS += -O3
setNoDeb:   objs

setDeb: CPPFLAGS += -DDEBUG=1
setDeb: CFLAGS += -g
setDeb: objs

objs: $(cFiles)
    $(CC) $(CFLAGS) $^ $(LIBS) -o $@

edited Jan 6, 2015 at 19:08

answered Mar 29, 2014 at 23:24

Chnossos

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