SystemVerilog dynamically accessing subarray

Question

I am getting an error to compile code line 9, so I am not sure how to dynamically access arrays. I have to build logic [255:0] from the received bytes. (Looks like I have to review data types of SystemVerilog :( ). Thanks in advance.

module test;

    task test_array (logic [7:0] B);
      static logic [255:0] l_ar_B;

      l_ar_B[7:0] = B;

      for(int i=0; i<32; i++)
        l_ar_B[(i*8+7) : (i*8)] = B; // Error-[IRIPS] Illegal range in part select
      $stop();

    endtask

    initial begin
      $display("Start");
      test_array(8'h11);
    end

endmodule

Greg · Accepted Answer · 2017-07-03 15:36:13Z

2

When using the range selection with [M : N] syntax, M and N must be be constants. You should use part-select addressing with the syntax [s +: W], where W is a constant for the width and s can be a variable indicating the starting bit position. The +: been around since IEEE Std 1364-2001 (Verilog 2001). See Indexing vectors and arrays with +:

for(int i=0; i<32; i++)
  l_ar_B[(i*8) +: 8] = B;

Since you are doing replication, you can use l_ar_B = {32{B}}; to get the same result in a singe step.

answered Jul 3, 2017 at 15:36

Greg

19.3k6 gold badges51 silver badges72 bronze badges

Sign up to request clarification or add additional context in comments.

2 Comments

albert waissman Over a year ago

Thanks. Very useful, did not found any where.

Greg Over a year ago

@albertwaissman , on this site "thanks" is best give by up-voting and ckecking the accept answer icon (if the answer satisfies your question and is the best answer). This helps others know you are not looking for more answers and helps those that have the same question as you.

Collectives™ on Stack Overflow

SystemVerilog dynamically accessing subarray

1 Answer 1

2 Comments

Your Answer

Linked

Hot Network Questions

Collectives™ on Stack Overflow

1 Answer 1

2 Comments

Your Answer

Sign up or log in

Post as a guest

Linked

Related