Verilog: value(s) does not match array range, simulation mismatch

Question

The following code synthesizes and simulates correctly as far as I can tell, but XST is still giving the following warning: value(s) does not match array range, simulation mismatch. Is there something I'm missing?

Tool used: Xilinx ISE Project Navigator (synthesizer:XST) FPGA: SPARTAN 3E

module error_example(
    input [47:0] data,
    input [2:0] sel,
    output [5:0] data_out
);

   assign data_out = data[sel*6 +: 6];

endmodule

WARNING:Xst:790 - "error_example.v" line 8: Index value(s) does not match array range, simulation mismatch.

Like I said, this works and I've done the math:

sel can have values from 0 to 7,

if sel is 0, then data_out = data[5:0] ...

if sel is 7, then data_out = data[47:42]

Should I do something differently here? Is this a bug in XST?

@nguthrie I'm pretty sure it was correct before your edits. If I wanted data_out = data[5:0] when sel = 0 then I would have wrote assign data_out = data[6*sel+5 -: 6]. It was much more convenient to use little endian format when I included this as part of a much larger module. — verigolfer
– verigolfer, Commented Mar 6, 2014 at 19:05
See section 11.5.1 of the spec. The first example shows a vector defined as [31:0] and then does a part select with [0 +: 8] and the result is bits [7:0]. I haven't used this feature very often since it is quite confusing. — nguthrie
– nguthrie, Commented Mar 6, 2014 at 19:36
Your original example had the data vector defines [lsb:msb] but you changed it to [msb:lsb] with your first edit. Hence the difference. — nguthrie
– nguthrie, Commented Mar 6, 2014 at 19:45
First hit on google says this message is sometimes invalid: forums.xilinx.com/t5/Synthesis/… — nguthrie
– nguthrie, Commented Mar 6, 2014 at 19:57
@nguthrie, good catch with the [lsb:msb] that does change the behavior of +:. +: means bits to the left, not ascending bits. — Greg
– Greg, Commented Mar 6, 2014 at 20:55

Morgan · Accepted Answer · 2014-03-06 09:20:13Z

5

I have created the example on EDAplayground, which runs without warning.

I would not normally use widths with parameters and if you do you might want to be consistent with the reg definitions.

Try:

parameter data = 48'h123456789ABC;
parameter [47:0] data = 48'h123456789ABC;

I do not think I have used parameters this way before but declaring a constant reg implies the same logic, which might avoid the warning.

reg [47:0] data = 48'h123456789ABC;

NB: It is good practise to use upper case for constants (parameter,localparam).

Alternatively convert to a case statement:

always @* begin
  case (sel)
    3'd0: data_out = 6'dx;
    3'd1: data_out = 6'dx;
    // ...
    default :  data_out = 6'd0;
  endcase
end

edited Mar 6, 2014 at 9:20

answered Mar 6, 2014 at 7:54

Morgan

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7 Comments

verigolfer Over a year ago

Regardless of the parameter, the warning still exists.. Edited my question.

Morgan Over a year ago

I would raise the issue with your tool vendor, the +:6 should guarantee the widths are the same. However this is a relatively new feature (2005) and support takes some time to propagate to all tools.

Greg Over a year ago

Actually, the +: is relatively old. It was introduced in IEEE Std 1364-2001 section 4.2.1 Vector bit-select and part-select addressing

Morgan Over a year ago

@Greg Your correct, I should double check my facts before stating them. Part 15 Of Sunburst Verilog 2001 also covers it quite well.

verigolfer Over a year ago

@Morgan I like your answer but it doesn't completely address my question. My data was really 768 bits wide (reduced for the example) and I didn't want to write 128 different cases.

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