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What's the memory order in this situation:

  1. ARM CPU connected to a PCIe NIC(Network Interface Card)
  2. The NIC write data and descriptor to ARM CPU memory, data and descriptor are normal memory.
  3. ARM CPU first poll descriptor to know their is a pkt received, then read the data.

My question:

  1. ARM CPU is weak order, The write of the CPU might be out of order, but what about the write of the NIC？NIC's write order is:write data, then write descriptor, but if the actual write order become:write descriptor then write data, it will cause mistake.
  2. I specify the situation to ARM architecture, because X86 is strong order, so I think NIC write to X86 is strong order too. is this right?
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  • Generally speaking no. You need to make your question way more specific if you want to get anything more detailed than that. Commented 18 hours ago
  • What do you mean by 'order'? Priority or the address is physically incrementing and what block size is committed to memory? A bus will have different arbitration rules for simultaneous accesses. A CPU 'order' to physical ram can be influence by ARM MMU pages. These can avoid cache or not. So, you need to say what ARM device you are talking about and what the page properties are. For systems that are not MMU-based, writes from the CPU will be in-order of machine code (but could be delayed). It seems to make no sense to talk about PCIe memory order? Commented 16 hours ago
  • So, if your question is about cache buffering and eviction, please give clues of this. It is not the ARM CPU, but the cache structure used by that CPU model which will allow someone to answer. For ARM systems with a cache and MMU enabled, pages maybe delegated to have different properties. So an OS may stipulate that the CPU will not cache data in L1/L2 for some cache pages (in the cases where the answer is not yes). Although 'order' according to what should be clarified. Normally it is memory order to machine code order. But PCIe has no machine code; PCIe can be host or device. Commented 16 hours ago
  • I maybe confusing. For an ARM system, the ARM can be a CPU with a PCIe host bus. DMA from the PCIe device to CPU memory is one question. Another question is that the ARM CPU is a PCIe device and a remote host has requested reads/writes, which could also use DMA, but I think the questions might be different. Please clarify what you mean. Commented 16 hours ago
  • add more information about the question, thanks Commented 9 hours ago
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