VHDL generic comparison and synthesis

Question

I have a problem when synthesizing code with generics : My entity is :

entity MyEntity is
  generic(
  OUTWIDTH : integer range 8 to 64;
  NBREG : integer range 2 to 8);
  port(
    port1 ....
    port2 ....
  );  
end entity;

architecture rtl of MyEntity is
constant KEEP_VAL : std_logic_vector(OUTWIDTH/8-1 downto 0) := (others=>'1'); -- used to compare my signal with (others=>'1')
signal keep : std_logic_vector((NBREG*OUTWIDTH/8)-1 downto 0);

begin

process(clk)
variable v1 : integer range 0 to NBREG-1
begin
if(rising_edge(clk)) then
   --SOME CODE
   ....
   ....
   -- The comparison I want to do :
  if(keep((v1+1)*(OUTWIDTH/8)-1 downto v1*(OUTWIDTH/8)) = KEEP_VAL) then  -- the line where the error appears
       -- DO sthg
end if;
end process;
end rtl;

To resume, I want to know if all the bits of a signal with a generic width (OUTWIDTH) are '1'. The previous code works well in simulations but doesn't whant to be synthesized. synplify for Libero : @E: CD289 : Expecting constant expression

I assume I could do it with a function (for loop on each bit and compare with '1') but is there an other "direct" option ?

Thank you.

It would be helpful if you edit the question to show the line that your error is associated with — scary_jeff
– scary_jeff, Commented Mar 24, 2017 at 14:30
the error is associated with the comparison line (the if condition) — lctdim
– lctdim, Commented Mar 24, 2017 at 14:32

QuantumRipple · Accepted Answer · 2017-03-24 14:47:49Z

4

Some synthesizers won't be able to use a non-constant value to dictate the range of a slice. One thing (of several) that you can do is map your array into a 2d array and use your non constant index to access what you want without any special slicing.

type keep_sliced_type is array(natural range <>) of std_logic_vector(outwidth/8-1 downto 0);
signal keep_sliced : keep_sliced_type(0 to nbreg-1);

...

g_map : for i in 0 to nbreg-1 generate
begin
    keep_sliced(i) <= keep(i*outwidth/8+outwidth/8-1 downto i*outwidth/8); --range is composed entirely of constants
end generate;

...

    if keep_sliced(v1)=keep_val then --replaces your erroring line

Furthermore, using variables is usually a bad idea, but I won't get too deep into that here. Fair warning, I just wrote this code in the answer box. It may have minor syntax errors.

answered Mar 24, 2017 at 14:47

QuantumRipple

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Comments

JHBonarius · Accepted Answer · 2017-03-24 14:35:53Z

1

Altough you question is not supported by a minimal complete verifiable example, thus it is difficult to properly help you, I can make an assumption.

First off: it is very easy to write VHDL that simulates correctly, but will not synthesize. You have to write VHDL specifically for synthesis.

The problem the synthesizer is giving is likely caused by the variable v1. It is kind of difficult to synthesize this line:

if(keep((v1+1)*(OUTWIDTH/8)-1 downto v1*(OUTWIDTH/8)) = KEEP_VAL)

This single line combines variable(=asynchronous) arithmetic (e.g. v1*(OUTWIDTH/8) with a multiplexer and a comparison operation. How would you want to see that realized in logic? First multiplex, Then compare? All compare and then select the correct result?

Likely it's better to separate the operations: implement a multiplexer (with a select using a signal, not a variable) and a comparator.

answered Mar 24, 2017 at 14:35

JHBonarius

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5 Comments

scary_jeff Over a year ago

In general, a range specified by a run-time varying quantity is not supported for synthesis.

lctdim Over a year ago

You are right, I though the problem was about the KEEP_VAL constant but it was about the keep variable. I changed the process to fix it.

QuantumRipple Over a year ago

@scary_jeff I once wrote a variety of implementions for a barrel shifter and synthesized them with XST and Vivado to test behaviour like this. The one that used non-constant ranges synthesized fine in XST but produced a similar error in Vivado.

JHBonarius Over a year ago

@QuantumRipple yes I have the same experience with Vivado not supporting the same as ISE. I have actually had some discussions with Xilinx on it. They've improved some things, not everything.

Paebbels Over a year ago

A variable is not asynchronous (that's terminology for clock behavior and timing analysis). The variable is not static. If I'm right a slice operations requires a static expression.

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