system verilog interface with function

Question

How can I add a function in an interface? I am trying to implement half adder using interface having function to calculate sum and carry.Following is my code for the same. When trying without functions it as running by using complemented lines.

module top_ha_interface;   
  ha_interface nh1();   
  ha h1(nh1);   
  ha_tb h2(nh1); 
endmodule 

interface ha_interface;   
  logic sum,c_out;   
  logic a,b;   
  function summ(a,b,output sum,c_out);     
    sum=a^b;     
    c_out=a&b;   
  endfunction   
endinterface 

module ha(ha_interface nh1);   
//  assign nh1.sum=nh1.a^nh1.b;   
//  assign nh1.c_out=nh1.a&nh1.b;   
  nh1.summ(nh1.a,nh1.b);  
endmodule 

module ha_tb(ha_interface nh1);   
  initial   
  begin         
    nh1.a=1'b1;         
    nh1.b=1'b0;     
    #10 $display($time,"ns\t",nh1.sum,nh1.c_out);         
    nh1.a=1'b1;         
    nh1.b=1'b1;     
    #20 $display($time,"ns\t",nh1.sum,nh1.c_out);         
    nh1.a=1'b0;         
    nh1.b=1'b0;     
    #30 $display($time,"ns\t",nh1.sum,nh1.c_out);   
  end 
endmodule

Karan Shah · Accepted Answer · 2016-02-07 09:46:10Z

1

Function is synthesizable, but that must be used, within any procedural block of verilog. (Like always or initial)

Tasks and void functions are called as statements within procedural blocks

So required modifications in your code :

module ha(ha_interface nh1);   
//  assign nh1.sum=nh1.a^nh1.b;   
//  assign nh1.c_out=nh1.a&nh1.b;   
  always @ (*)
    nh1.summ(nh1.a,nh1.b, nh1.sum, nh1.c_out);  
endmodule

answered Feb 7, 2016 at 9:46

Karan Shah

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9 Comments

NIKHIL ARORA Over a year ago

Thanks It's working now. Can you please tell me how can I improve my SV skills? Is it possible to finish UVM within a month? I will start working on UVM from tomorrow onward and I study for 12 hours daily.

Karan Shah Over a year ago

@NIKHILARORA : You can read book like "SV For Verification" by Chris Spear, System Verilog LRM. For UVM, you should read "UVM Cookbook" and also you can watch videos on Verification Academy. Btw, if you are convinced with the answer, you can accept my answer, also you can upvote it, if you want.

Greg Over a year ago

IEEE Std 1800-2012 is the SystemVerilog LRM. The (Verification Academy)[verificationacademy.com/] is a good resource; I'd recommend the video lessons over the UVM Cookbook. Neither are perfect, but I find the the cookbook more OVM oriented (a predecessor methodology) has more confusing subtle typos that make learning more painful.

NIKHIL ARORA Over a year ago

@ Greg and Karan: Are you sure that I can finish UVM in a month by studying 12 hours in a day?

Karan Shah Over a year ago

@NIKHILARORA : That noone can assure, how much time a person will take to understand any specific thing. But yeah one month, with dedicated efforts, you can learn many required things of UVM.

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