easiest way to connect unpacked array on module interface in systemverilog

Question

Here is an example below

module a_mod ( u );
input bit [2:0] u [1:0];
...
endmodule

module b_mod ();

bit [2:0] c1, c2;
a_mod a_mod_inst ( 
  .u ( {c1,c2} ) // won't work
);

endmodule

What's the easiest way of doing the hookup such that u[0] == c2 and u[1] == c1 ?

BTW, I know I can do what I show below, but looking for a more elegant alternative

bit [2:0] tmp_u [1:0];
assign tmp_u[0] = c2;
assign tmp_u[1] = c1;

a_mod a_mod_inst (
.u ( tmp_u )  // works for sure
);

Greg · Accepted Answer · 2013-04-22 22:18:20Z

3

Try:

bit [2:0] c1, c2;
a_mod a_mod_inst ( 
  .u ( '{c1,c2} ) // note the single quote before the open curly bracket
);

See IEEE1800-2012 Section 10.9. '{ is used for assigning or passing unpacked arrays.

answered Apr 22, 2013 at 22:18

Greg

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