How can I write an 8-bit array as input of a module in systemverilog

Question

I'm new to verilog and I use Modelsim. How can I write an 8-bit array as input of a module in systemverilog that its bits are bits of another array?

something like this:

module cmp2(input[1:0] A,B, output GT,EQ);
    mux8to1 M1(8'b0~B[0]11000B[0], 3'bB[1]A[1]A[0], GT);

mux8to1 is defined in following format of inputs:

module mux8to1(input[0:7]a, input[2:0]s, output w);

compile of "cmp2" fail with errors:

Illegal digit for specified base in numeric constant.

near "[": syntax error, unexpected '[', expecting ')'.

I will appreciate any advice of you guys on help me to solve this.

Rich Maes · Accepted Answer · 2017-03-08 04:28:31Z

There are several problems with this line, mux8to1 M1(8'b0~B[0]11000B[0], 3'bB[1]A[1]A[0], GT);

For the first term, it appears you are trying to do a bit-wise negation for the input. You say B[0]11000B[0], is not a legal bit vector. Did you mean {B[0],5'b11000,B[0]}? This would create a 7 bit vector, not 8.

Also not sure what would be intended if you assigned 8'b0~{B[0],5'b11000,B[0]} as the bit-wise negation would affect the later term. I think you were trying to say, make an 8 bit vector, and needed an extra zero to do that. Perhaps you really meant, {1'b0,B[0],5'b11000,B[0]}, which would be an 8 bit vector.

The second input, perhaps you meant {B[1],A[0],A[1]} This would be a 3 bit vector.

Taken as a whole, it would look something like this

mux8to1 M1({1'b0,B[0],5'b11000,B[0]},{B[1],A[0],A[1]},GT);

Is that what you were looking for?

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