Is processor cache flushed during context switch in multicore?

Question

Recently, I discussed why there is a volatile mark at seq in Java Actors demo

@volatile private var seq = 0L
private def nextSeq: Long = {
  val next = seq
  seq += 1
  next
}

One answer was that threads can be migrated and variables lost (other cores will have incoherent values in their private caches). But, you not normally mark every variable with volatile to enable multicore execution. So, cores must flush the caches whenever context is switched. But, I cannot find this statement pronounced explicitly anywhere. Everybody, eg. Wikipedia, only care about registers and stack memory

The state of the process includes all the registers that the process may be using, especially the program counter, plus any other operating system specific data that may be necessary. This data is usually stored in a data structure called a process control block (PCB), or switchframe. In order to switch processes, the PCB for the first process must be created and saved. The PCBs are sometimes stored upon a per-process stack in kernel memory (as opposed to the user-mode call stack), or there may be some specific operating system defined data structure for this information.

What do we have in reality regarding migrating the general purpose data/variables?

Cache coherence mechanisms will usually mean there's no need to flush a cache. — Damien_The_Unbeliever
– Damien_The_Unbeliever, Commented Jun 11, 2015 at 7:50
Thanks. Probably somebody will be able to explain how Cache coherence is related to the thread migration. — Val
– Val, Commented Jun 11, 2015 at 9:52
Whenever there is any sort of context switch the OS will save its state such that it can be restarted again on any core (assuming it has not been tied to a spefic core using a ocessor affinity function). — Olof Forshell
– Olof Forshell, Commented Jun 21, 2015 at 19:29

Olof Forshell · Accepted Answer · 2015-06-21 19:37:41Z

9

Whenever there is any sort of context switch the OS will save its state such that it can be restarted again on any core (assuming it has not been tied to a specific core using a processor affinity function).

Saving a state that for some reason or other is incomplete defeats the entire purpose of threading or processing, therefore the caches are flushed as part of the switch.

Volatile has nothing whatsover to do with context switching. It merely tells the compiler that the memory location is subject to change without notice and therefore must be accessed each time the source code dictates it i e the usual compiler behaviour of optimizing accesses to memory locations does not apply to the volatile-declared location.

answered Jun 21, 2015 at 19:37

Olof Forshell

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pveentjer Over a year ago

There are fences on 2 levels; hardware and compiler. The compiler fences will prevent the compiler to optimize out loads/stores. But fences on hardware level are equally important to make sure that other loads and stores are properly ordered with respect to a volatile load/store.

Almas Abdrazak · Accepted Answer · 2021-12-24 23:27:46Z

0

other cores will have incoherent values in their private caches

So by default each processor has a thing called MESI protocol which basically force each cpu core to flush the variable once it was modified by single processor in order to keep the variable in consistent state. The thing is it's really costly so Java compiler makes an assumption that all variables will be used by single core instead. The volatile keyword prohibit compiler to make this optimization .

answered Dec 24, 2021 at 23:27

Almas Abdrazak

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pveentjer Over a year ago

Modern CPU caches are always coherent; which is done using a cache coherence protocol e.g. MESI or some variation like MESIF or MOESI. The cache coherence protocol will prevent that CPU's sees loads and stores, to a single address, out of order. There is no flushing to memory involved. Volatile will prevent that the compiler will optimize-out a load or a store; so it will prevent 'caching' a value in a register. But it will not prevent that a cache line, containing a volatile variable, is being cached in the CPU cache.

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