Variable assignment in SystemVerilog generate statement

Question

I have created a simple module that I replicate several times using the Verilog generate statement. However, it seems that the generate statement somehow effects variable assignment in the module. Here's the code:

module test();
  timeunit      10ns;
  timeprecision 1ns;

  wire[3:0] out; 
  reg[3:0] values[0:4] = {5, 6, 7, 8, 9};

  logic clk;

  generate
    genvar i;
    for (i=0; i < 5; i++)  begin: M1
      MUT mut(
      .out,
      .in(values[i]),
      .clk
      );
    end
  endgenerate

  initial begin
    #1 clk = 0;

    $monitor("%b %b %b %b %b\n", M1[0].mut.out, M1[1].mut.out, M1[2].mut.out, M1[3].mut.out, M1[4].mut.out);

    #10 $stop;
  end

  always #1 clk++;
endmodule

module MUT(output [3:0] out, input [3:0] in, input clk);

 reg[3:0] my_reg[0:7];

 assign out = my_reg[7];

 always @(posedge clk) begin
    my_reg[7] <= in; //5
 end

endmodule

The expected output of this test program would be 0101 0110 0111 1000 1001, however the output I get is xxxx xxxx xxxx xxxx. It seems that the values in the values variable in the test module are not getting assigned to the out variable in the MUT module. However, when I replace my_reg[7] <= in; with say, my_reg[7] <= 5;, the code works as expected. The code also works when I assign directly to out (after declaring it as register) i.e. out <= in;. There's no problem if I replicate the MUT modules 'manually' without using any generate statements.

Jean · Accepted Answer · 2014-08-29 15:35:07Z

3

You are not connecting the outputs to separate wires. So they are implicitly tied together(like how it did for clock) resulting multiple drivers for a bit.

Just add

wire[3:0] out[0:4]; 

  generate
    genvar i;
    for (i=0; i < 5; i++)  begin: M1
      MUT mut(
      .out(out[i]),  // Connect to different wires
      .in(values[i]), 
      .clk
      );
    end
  endgenerate

edited Aug 29, 2014 at 15:35

answered Aug 29, 2014 at 15:19

Jean

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Comments

Eisenfrost · Accepted Answer · 2014-08-29 14:58:21Z

0

Try to initialize clk variable with 0.

edited Aug 29, 2014 at 14:58

answered Aug 29, 2014 at 13:34

Eisenfrost

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