Overflow in SystemVerilog constraints

Question

Integer types in SystemVerilog, as in most languages, wrap around on overflow. I was wondering if this is also true in constraints. For example:

class Test;
  rand bit [3:0] a;
  rand bit [3:0] b;

  constraint c { a + b <= 4'h6; }
endclass;

When randomizing an object of this class, is it possible to get a solution where a == 7 and b == 12, which would satisfy the constraint since 7 + 12 = 19 which wraps around to 3, and 3 is less than 6?

If so, would it help to formulate the constraint as

constraint c { a + b <= 6; }

where 6 is a 32-bit signed int and the sum is forced to be calculated with 32-bit precision? (This of course is not a solution if the random variables are of type int)

dave_59 · Accepted Answer · 2017-10-06 15:11:37Z

1

You are correct. Expression evaluation is identical whether you are inside a constraint or not. In addition to overflow, you also need to be concerned about truncation and sign conversion. Integral expressions are weakly typed in SystemVerilog.

answered Oct 6, 2017 at 15:11

dave_59

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